Allow a new cpu_debugging flag to be passed to the constructor to
enable in-circuit live debugging of the softcore under gdb.
Signed-off-by: Sean Cross <sean@xobs.io>
Add support for debugging the CPU, and gate it behind a new cpu_debug
parameter. With this enabled, a simple Wishbone interface is provided.
The debug version of the core adds two 32-bit registers to the CPU.
The register at address 0 indicates status, and is used to halt
and reset the core.
The debug register at address 4 is used to inject opcodes into the
core, and read back the result.
A patched version of OpenOCD can be used to attach to this bus via
the Litex Ethernet or UART bridges.
Signed-off-by: Sean Cross <sean@xobs.io>
The upstream vexriscv repo now generates both the current VexRiscv.v
softcore, as well as VexRiscv-Debug.v. This -Debug varient exposes
their specialized debug bus that allows for attaching a modified version
of openocd.
Sync the litex repo with the upstream version to take advantage of debug
support.
Signed-off-by: Sean Cross <sean@xobs.io>
The BIOS builds just fine on Windows, but afterwards tries to run
`chmod`. This command does not exist on Windows, and is unnecessary.
Add a conditional guard to prevent this command from running on Windows.
Signed-off-by: Sean Cross <sean@xobs.io>
Before;
```
"/usr/local/lib/python3.5/dist-packages/litex-0.1-py3.5.egg/litex/soc/integration/soc_core.py",
line 258, in get_csr_dev_address
return self.csr_map[name]
KeyError: 'core'
```
Now;
```
Traceback (most recent call last):
File "XXXX/github/enjoy-digital/litex/litex/soc/integration/soc_core.py", line 259, in get_csr_dev_address
return self.csr_map[name]
KeyError: 'ddrphy'
The above exception was the direct cause of the following exception:
Traceback (most recent call last):
...
File "XXXX/github/enjoy-digital/litex/litex/soc/interconnect/csr_bus.py", line 199, in scan
mapaddr = self.address_map(name, None)
File "XXXX/github/enjoy-digital/litex/litex/soc/integration/soc_core.py", line 269, in get_csr_dev_address
) from e
RuntimeError: Unable to find ddrphy in your SoC's csr address map.
Check BaseSoC.csr_map in XXXX/github/enjoy-digital/litex/litex/boards/targets/arty.py
Found l2_cache, timer0, ddrphy2, buttons, sdram, identifier_mem, uart, uart_phy, leds, crg in the csr_map
```
Sean Cross
Florent Kermarrec
bunnie
Deano Calver
Dolu1990
Tim 'mithro' Ansell