Sebastien Bourdeauducq
|
0caac2246d
|
Use new 'specials' API
|
2013-02-24 13:07:25 +01:00 |
|
Sebastien Bourdeauducq
|
5649e88a90
|
Use Mibuild
|
2013-02-11 18:23:06 +01:00 |
|
Sebastien Bourdeauducq
|
c86dd3cbef
|
Define clock domains instead of passing extra clocks as regular signals
|
2012-09-11 00:21:07 +02:00 |
|
Sebastien Bourdeauducq
|
5931c5eb59
|
Basic support for new clock domain and instance API
|
2012-09-10 23:47:06 +02:00 |
|
Sebastien Bourdeauducq
|
3a02524cc7
|
VGA framebuffer connections
|
2012-06-17 13:41:26 +02:00 |
|
Sebastien Bourdeauducq
|
4e18e45686
|
Add Ethernet MAC
|
2012-05-20 00:30:03 +02:00 |
|
Sebastien Bourdeauducq
|
19b1cc2529
|
Remove uses of pads, new constraints system
|
2012-04-02 19:22:17 +02:00 |
|
Sebastien Bourdeauducq
|
b4e041ecf1
|
s6ddrphy: write path OK in simulation
|
2012-02-20 23:55:20 +01:00 |
|
Sebastien Bourdeauducq
|
f35cd4a85b
|
Prepare for new DDR PHY
|
2012-02-19 18:43:42 +01:00 |
|
Sebastien Bourdeauducq
|
5d1dad583b
|
Connect DDR PHY
Doesn't do much for the moment, just to check synthesis/P&R.
|
2012-02-17 11:04:44 +01:00 |
|
Sebastien Bourdeauducq
|
204452b0d3
|
m1crg: make clock feedback pin bidirectional
|
2012-02-16 18:35:44 +01:00 |
|
Sebastien Bourdeauducq
|
72f9af9d90
|
Generate all clocks for the DDR PHY
|
2012-02-16 18:02:37 +01:00 |