Commit Graph

7384 Commits

Author SHA1 Message Date
Hans Baier 5fd1cae618 lattice/programmer.py: Add iCESugar programmer 2021-05-07 10:55:48 +07:00
Florent Kermarrec 34ed5672c3 tools/litex_server/litex_term: Add --jtag-chain argument. 2021-05-06 15:41:25 +02:00
Florent Kermarrec 24105f12d5 openocd/stream: Expose chain parameter. 2021-05-06 15:25:18 +02:00
Florent Kermarrec aea1e7fb20 jtag/jtagbone: Expose chain parameter. 2021-05-06 14:58:47 +02:00
Florent Kermarrec 3ce5f3867a cores/video/VideoS7GTPHDMIPHY: Add refclk support (None, Differential or Single-Ended). 2021-05-06 10:50:29 +02:00
Florent Kermarrec bfb90f5625 soc/cores/video: Add VideoS7GTPHDMIPHY (7-Series HDMI PHY over GTPs).
Validated on Decklink Mini 4K Monitor at 1080p60 (should allow UHD/4K), still
some fixed things, but should provide a good basis to go further...
2021-05-05 18:12:10 +02:00
Florent Kermarrec d6084cd1f9 CHANGES: Add 2021.04 changes. 2021-05-03 11:59:42 +02:00
Florent Kermarrec 1d21a90076 software/liblitespi: Fix compilation warning. 2021-05-03 10:34:45 +02:00
enjoy-digital c3f4da4376
Merge pull request #902 from tcal-x/radiant-lse
Add 'lse' as a --synth-mode alternative with Radiant toolchain.
2021-05-03 10:13:52 +02:00
Tim Callahan dcd13d27ef Add 'lse' as a --synth-mode option with Radiant.
Signed-off-by: Tim Callahan <tcal@google.com>
2021-05-01 21:12:56 -07:00
enjoy-digital fb8f45be73
Merge pull request #901 from stffrdhrn/litex-sdcard-irq
integration/soc: Wire up the sdirq to the CPU
2021-04-30 12:30:35 +02:00
Florent Kermarrec 59b968decc cores/clock/gowin_gw1n: Fix indent. 2021-04-30 12:22:59 +02:00
Florent Kermarrec 5dc3ad3b29 soc/cores/spi/SPISlave: Minor cleanup. 2021-04-30 12:16:49 +02:00
Florent Kermarrec 75bb78a413 cores/clock: Add initial Gowin GW1N PLL support.
For now limited to one output clock and not supporting phase/duty cycle adjustements.
2021-04-30 11:31:04 +02:00
Florent Kermarrec fefc5aae66 cores/video/VideoVGAPHY: Add optional clk support.
Some LCDs displays are almost VGA compatible (no DE, active low hsync/vsync)
but require the clock.
2021-04-29 11:50:04 +02:00
Florent Kermarrec 87ebdea5a7 software/libliteeth: Add optional ETH_PHY_NO_RESET support to allow disabling software reset.
Un-wanted when using the Hybrid LiteETHMAC since interrupt the hardware UDP/IP stack.
2021-04-29 11:50:00 +02:00
Stafford Horne a9e935e61a tools/litex_json2dts: Add interrupt settings for sdcard 2021-04-29 17:52:17 +09:00
Stafford Horne dc1a4c5380 integration/soc: Wire up the sdirq to the CPU
I am working on testing out the patches from:
 https://github.com/litex-hub/linux/pull/8

These linux patches take advantage of the sdcard interrupt to track when
transfers finish.  However, it seems the interrupt is not being
connected to the CPU.

This patch does that by allowing us to directly register and
EventManager module with the irq handler.
2021-04-29 17:18:51 +09:00
Tim Ansell 11f091d4cf
Merge pull request #900 from stffrdhrn/rom-to-128k
integration/soc_core: Increase default ROM size to 128K
2021-04-28 15:28:19 -07:00
Stafford Horne 2f96cf021c integration/soc_core: Increase default ROM size to 128K
With recent BIOS changes the default rom size on the mor1kx built just
passes over the 64k boundary and the build fails.  Since the 128K
default is a soft limit and the ROM gets resized to the actual ROM
requirements this should be relatively safe.

Note, that if a RW rom is configured the full 128kb will be allocated.

Fixes: #893
2021-04-29 06:52:49 +09:00
Florent Kermarrec 9098f5553c software/liblitedram: Add liblitedram prefix to includes (to use copy of bist.c/sdram.c externally). 2021-04-28 17:21:04 +02:00
Florent Kermarrec bb355a773a integration/soc/video: Allow passing timings as str or tuple (name, dict).
When passed as str, the timing dict will be extracted from litex.soc.cores.video.video_timings.
When passed as tuple, custom dict will be directly passed to VTG.
2021-04-28 16:58:11 +02:00
Florent Kermarrec c4e8e44cd9 cores/video/VideoTimingGenerator: Allow passing custom dict as default_video_timings.
Allow only listing the classical video timings in the core and let user provide the timings
specific to other configurations.
2021-04-28 16:56:28 +02:00
enjoy-digital da1092d9c0
Merge pull request #896 from danc86/nodefaultlibs
soc/software: link with compiler instead of ld
2021-04-28 15:44:49 +02:00
Florent Kermarrec f7b615ffab software/liblitedram/sdram.c: Avoid direct ddrphy_wdly_dq_rst during DQ-DQS training on Ultrascale/Ultrascale+ (seems to cause issue on some configurations/modules).
Also add a delay to be similar to read_leveling reset/inc functions.
2021-04-28 14:42:41 +02:00
Florent Kermarrec dc4f9772ba software/liblitedram/sdram.c: Move common centering functions to separate section. 2021-04-28 14:15:48 +02:00
Florent Kermarrec 19d16fa27f software/liblitedram/sdram/sdram_write_leveling_find_cmd_delay: Only update best_count when error < best_error. 2021-04-28 11:23:34 +02:00
Florent Kermarrec c50989be8e software/liblitedram/sdram: Add sdram_tck_taps variable and use it internally to avoid un-needed accesses to CSRs. 2021-04-28 11:22:07 +02:00
Florent Kermarrec 87c0e30cef software/liblitedram/sdram.c: Remove residual wrap around code, fix some spaces/tabs. 2021-04-28 10:45:35 +02:00
Florent Kermarrec 74c42a55e2 tools/litex_json2dts/framebuffer: Use framebuffer_base. 2021-04-27 18:59:54 +02:00
Florent Kermarrec a3f3d8f08f software/liblitedram/sdram: Fix compilation warning. 2021-04-27 16:33:40 +02:00
enjoy-digital c4195254ed
Merge pull request #897 from antmicro/jboc/dq-dqs-training
software/liblitedram: use single iteration of dq-dqs training
2021-04-27 13:30:03 +02:00
Jędrzej Boczar ad23130a9a software/liblitedram: use single iteration of dq-dqs training 2021-04-27 10:54:32 +02:00
Dan Callaghan 020466a43e soc/software: link with compiler instead of ld
The linker does not actually recognise -nodefaultlibs, that is a compiler
option.

Prior to binutils 2.36, ld treated -nodefaultlibs as a string of short
options and ignored them as unrecognised. Starting from binutils 2.36, it
reports an error instead:

    riscv64-unknown-elf-ld: Error: unable to disambiguate: -nodefaultlibs (did you mean --nodefaultlibs ?)

See also: https://sourceware.org/bugzilla/show_bug.cgi?id=27050

Fixes #825.
2021-04-27 15:36:13 +10:00
Florent Kermarrec 4c26dbe98f cores/cpu/microwatt: Re-map csr/xics and keep the lower 128MBs for the SoC IO auto-allocation. 2021-04-26 18:37:40 +02:00
Florent Kermarrec 9a82fd1d54 tools/litex_sim: Use automatic ethmac allocation. 2021-04-26 18:33:50 +02:00
Florent Kermarrec 48ec20e2ef software/liblitedram/sdram: Remove wraps around in sdram_leveling_center_module.
Adding wraps around capability will have to be discussed, if implemented this has to
be done very carefully since there are no relation between the total delay that can
be compensated through the I/O-DELAYs and the SDRAM clock period.

As implemented, it also produced confusing values in the logs:

m0:0 m1:0
Read leveling:
  m0, b0: |00000000000000000000000000000000| delays: -
  m0, b1: |00000000000011111111111111100000| delays: 19+-07
  m0, b2: |00000000000000000000000000001111| delays: 14+-17
  m0, b3: |00000000000000000000000000000000| delays: -
  m0, b4: |00000000000000000000000000000000| delays: -
  m0, b5: |00000000000000000000000000000000| delays: -
  m0, b6: |00000000000000000000000000000000| delays: -
  m0, b7: |00000000000000000000000000000000| delays: -
  best: m0, b01 delays: 19+-07
  m1, b0: |00000000000000000000000000000000| delays: -
  m1, b1: |00000000000011111111111111000000| delays: 19+-07
  m1, b2: |00000000000000000000000000001111| delays: 15+-17
  m1, b3: |00000000000000000000000000000000| delays: -
  m1, b4: |00000000000000000000000000000000| delays: -
  m1, b5: |00000000000000000000000000000000| delays: -
  m1, b6: |00000000000000000000000000000000| delays: -
  m1, b7: |00000000000000000000000000000000| delays: -
  best: m1, b01 delays: 19+-07
Switching SDRAM to hardware control.

--> 14+-17 and 15+-17 are confusing.
2021-04-26 17:27:27 +02:00
enjoy-digital a6c5fd7aed
Merge pull request #891 from antmicro/crosslink-nx-fix-sdr-buffers
Lattice Crosslink NX: Fix clock port names in SDR{in/out} Impl
2021-04-26 11:19:44 +02:00
enjoy-digital 65a4886b72
Merge pull request #892 from jluebbe/bios
bios: support passing tftp filename to the 'netboot' command
2021-04-26 10:59:53 +02:00
Jan Luebbe f4c9bf0666 bios: support passing tftp filename to the 'netboot' command
Signed-off-by: Jan Luebbe <jlu@pengutronix.de>
2021-04-25 20:45:03 +02:00
Karol Gugala 54f729fbc1 Lattice: Fix port names in SDR{in/out} Impl
Signed-off-by: Karol Gugala <kgugala@antmicro.com>
2021-04-25 19:47:30 +02:00
Florent Kermarrec 22d763ee11 tools/litex_sim: Remove self.add_csr calls no longer required. 2021-04-23 19:33:51 +02:00
Florent Kermarrec 8c8c1fe6e0 tools/litex_sim: Fix cpu in configuration (allow list of supported CPU to be listed when invalid cpu_type is provided). 2021-04-23 19:16:18 +02:00
Florent Kermarrec 116c2f1549 cores/cpu: Cosmetic cleanups. 2021-04-23 16:16:31 +02:00
Florent Kermarrec fe7029a7e0 software/liblitedram: Add missing read window re-centering after selecting bitslip in Write DQ-DQS training. 2021-04-22 17:08:20 +02:00
enjoy-digital 447d2648e8
Merge pull request #884 from antmicro/jboc/dq-dqs-training
Write DQ-DQS training
2021-04-22 17:08:08 +02:00
Florent Kermarrec 0ed7852779 tools/litex_term: Add time.sleep on BridgeUART to avoid high CPU usage. 2021-04-22 17:07:33 +02:00
Florent Kermarrec 75045914b4 global: Bump copyright year. 2021-04-22 17:07:29 +02:00
Florent Kermarrec b55af2156b soc/add_sdcard: Fix cmd_done signal. 2021-04-21 13:38:00 +02:00
enjoy-digital 482bd61ea5
Merge pull request #887 from paulusmack/master
integration/soc/add_sdcard: Add an interrupt for command completion
2021-04-21 11:00:55 +02:00