a08c5201ad
Efinix: improve ifacewriter + misc
2021-09-28 18:06:57 +02:00
45961f733b
Efinix: instance of dbparser class now in platform
2021-09-28 18:06:23 +02:00
b2e09832e5
Efinix: dbparser, add get_gpio_instance_from_pin
2021-09-28 18:04:49 +02:00
32f4d246f4
Efinic ConstraintManager improve delete method
2021-09-28 18:04:27 +02:00
5a35aa9df6
software/libliteeth: Fix missing prototype warnings.
2021-09-28 17:46:23 +02:00
7bf6db5f9d
README: Add meson package install.
2021-09-28 16:27:30 +02:00
9a931324c2
get_data_mod: Update pip to pip3 to avoid issues on systems with Python2 still installed.
2021-09-28 16:27:13 +02:00
a5b3ab1bc9
Merge pull request #1051 from antmicro/picolibc-updates
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Picolibc updates
2021-09-28 16:01:29 +02:00
9f1108c2fc
libc: refactor picolibc build deps
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Signed-off-by: Karol Gugala <kgugala@antmicro.com>
2021-09-28 15:17:30 +02:00
b9c4d7ba51
libc: add _impure_ptr definition
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Signed-off-by: Karol Gugala <kgugala@antmicro.com>
2021-09-28 15:17:08 +02:00
22f50ec7ff
libc: add errno include
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This solves missing `__errno` symbol linker errors
Signed-off-by: Karol Gugala <kgugala@antmicro.com>
2021-09-28 15:16:34 +02:00
a588c3b830
software/libc: Disable Atomics support on fgetc/ungetc since seems broken (at least on Rocket).
2021-09-28 14:51:02 +02:00
99d8bbc3bc
Merge pull request #1050 from antmicro/fix-litex_setup_url
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Revert litex_setup_url change
2021-09-28 14:28:29 +02:00
061b89beff
cpu/picolibc: Add family property to CPUs and directly use it for picolibc.
2021-09-28 14:20:13 +02:00
b451f102c6
software/libc/stdio: Simplify/Cleanup.
2021-09-28 14:04:24 +02:00
12c93ea895
litex_sim: Generate gtkw_savefile only with --trace.
2021-09-28 13:32:12 +02:00
c0e7e3acd3
Revert litex_setup_url change
2021-09-28 12:35:20 +02:00
782744bae3
tools/litex_sim/generate_gtkw_savefile: Check main_ram presence.
2021-09-28 10:02:17 +02:00
de738e153d
tools/litex_sim: Avoid double build iteration with pre_run_callback function.
2021-09-28 09:58:43 +02:00
c98c777bed
integration/builder: Avoid picolibc/compiler_rt dependencies when not using the LiteX BIOS & minor cleanups.
2021-09-28 08:57:49 +02:00
29fb1c48d0
Merge pull request #1046 from antmicro/libc-deps
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software: libc: fix Makefile dependecies
2021-09-27 14:56:25 -07:00
d101ef7ed0
software: libc: fix Makefile dependecies
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Signed-off-by: Karol Gugala <kgugala@antmicro.com>
2021-09-27 23:05:54 +02:00
01a906add7
software/liblitesdcard: Fix compilation with picolibc.
2021-09-27 18:56:18 +02:00
727d898a6c
software/libliteeth: Update/Fix compilation with picolibc.
2021-09-27 18:54:28 +02:00
54623dbe26
litex_setup: Update picolibc url (now on litex-hub).
2021-09-27 18:15:10 +02:00
7119dd8098
Merge pull request #1023 from lschuermann/dev/litex-sim-gmii-xgmii
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litex_sim: add support for simulated GMII & XGMII, rewrite XGMII module
2021-09-27 17:48:44 +02:00
87f7f3bc45
Merge branch 'master' into dev/litex-sim-gmii-xgmii
2021-09-27 17:47:26 +02:00
9ab82cacda
soc/add_ethernet/etherbone: Fix conflicts/Update.
2021-09-27 17:43:39 +02:00
17abdfd12d
Merge pull request #1043 from enjoy-digital/rocket-remove-reset-inserter
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cpu/rocket/core: Remove ResetInserter on adapters.
2021-09-27 16:34:46 +02:00
49f8652f91
ci: Install meson (now required by picolibc).
2021-09-27 16:19:56 +02:00
746d698b49
litex_setup.py: Revert LiteX url.
2021-09-27 16:15:16 +02:00
3d32ac3d2e
software: Avoid libase renaming to libutils/libcomm and keep readchar/putsnonl retro-compatibility.
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We'll maybe do it but that's probably not the right time. We have to make
the picolibc switch as smooth as possible for users (and so avoid update
as much as possible).
In the long term, it would be good to provide a LiteX C SDK, so we'll make
eventual changes when doing this.
2021-09-27 16:15:13 +02:00
ae1d43b965
software/libc/Makefile: Use proper CFLAGS to avoid picolibc warnings and cleanup a bit Makefile.
2021-09-27 16:14:55 +02:00
c0b54f0105
Merge pull request #976 from antmicro/libbase-replacement
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Replace libbase with picolibc
2021-09-27 16:05:24 +02:00
944732aa19
soc/add_sdram: Also remove ResetInserter on axi.AXI2Wishbone.
2021-09-27 15:46:19 +02:00
06ff638f7a
efinix: rgmii: fix, it's in a working state
2021-09-27 10:11:58 +02:00
1ea0797c82
efinix: ifacewriter: fix DRIVE_STRENGTH and REFCLK_FREQ
2021-09-27 10:11:00 +02:00
ce0551b44a
cpu/rocket/core: Remove ResetInserter on adapters.
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Previously, the SoCController was only reseting the CPU, which required adding
these ResetInserters. Now that the SoCController resets both CPU and peripherals
these ResetInserters are redundant and no longer useful.
2021-09-27 09:05:46 +02:00
179a8018b3
efinix: RGMII phy should be operational (no tested)
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PLL infrastructure should be complete now.
We can also use DDIO input and outputs.
However, there is problem (bug) during P&R:
ERROR(1): [Line 52] Block auto_eth_tx_delayed_clk is
an output pad but sub-block 1 is not an output pad location.
Inderface Designer validation doesn't report any problem.
I have a test project with the same configuration (I compared
the reports for blocks configuration) and it works.
2021-09-23 17:21:17 +02:00
c43132f81f
Merge pull request #1040 from gsomlo/gls-rocket-smp
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Rocket SMP support
2021-09-23 10:56:06 +02:00
07e47d9357
cpu/rocket: add quad-core (smp) variants
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- 4-core "full" (fpu-enabled) variants with double, quad mem. bus width
- 4-core "linux" (fpu-less) variant with single (64-bit) mem. bus width
2021-09-22 16:59:04 -04:00
901b19828c
cpu/rocket: include core count as per-variant parameter
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Repurpose (and rename to `CPU_SIZE_PARAMS`) the current
`AXI_DATA_WIDTHS` array. In addition to axi widths for
mem and mmio ports, also include each variant's number
of cores, to facilitate dynamically generated per-core
signals.
2021-09-22 16:58:11 -04:00
e6aaa40d2d
cpu/rocket: bios support for SMP
2021-09-22 13:51:18 -04:00
2bc8124114
cpu/rocket: crt0, boot-helper: use temp. registers (cosmetic)
2021-09-22 13:51:18 -04:00
1d302c56da
Merge pull request #1041 from gsomlo/gls-vex-smp-fix
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cpu/vexriscv_smp/crt0.S: only boot core should run data_init
2021-09-22 19:35:47 +02:00
60c6077c32
remote/comm_udp: Add padding bytes to Etherbone probe.
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Now required with LiteEth dropping exceeding payload.
2021-09-22 16:52:08 +02:00
23b2ac2013
cpu/vexriscv_smp/crt0.S: only boot core should run data_init
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Also, no need for non-boot cores to `call smp_slave`, it's the
immediately following instruction for them already.
2021-09-22 09:55:20 -04:00
109dbd1d62
efinity: small fixes
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- do not include *.vh files in project,
- add self.options to class EfinityToolchain
- remove unconditional call to self.ifacewriter.add_ddr_xml
2021-09-22 09:53:27 +02:00
b24475b07d
Add an hacked no we memory for Efinix
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Efinity synthesizer cannot infer RAM blocks with write enable.
In order to workaround this (at least for the Litex SoC intergrated
RAM/ROM) a dirty modified Memory class has been created.
This class needs to be rewrite !
2021-09-22 09:47:51 +02:00
027f7aa645
tools/litex_json2dts_linux: Fix typo.
2021-09-21 14:32:20 +02:00
Franck Jullien
Florent Kermarrec
Karol Gugala
Michal Sieron
Tim Ansell
Gabriel Somlo