Sebastien Bourdeauducq
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2cd80990e4
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minicon: fix use of phy phases
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2014-11-27 22:13:17 +08:00 |
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Sebastien Bourdeauducq
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8418ccafdc
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minicon: remove unused signals and fix indent
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2014-11-27 22:12:05 +08:00 |
Yann Sionneau
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cf92821fcf
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Refactor directory hierarchy of sdram phys and controllers
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2014-11-27 22:09:10 +08:00 |
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Yann Sionneau
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f33b285af1
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Minicon: small SDRAM controller
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2014-11-27 22:09:03 +08:00 |
Florent Kermarrec
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5202f89db1
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ethmac/last_be: remove fake signal (fixed in Migen)
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2014-11-21 14:48:17 -08:00 |
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Sebastien Bourdeauducq
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b7028848b2
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ethmac: use new EndpointDescription API
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2014-11-20 22:32:32 -08:00 |
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Sebastien Bourdeauducq
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33530e0921
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ethmac: style/renaming
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2014-11-20 18:01:48 -08:00 |
|
Florent Kermarec
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603c2641bb
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new Ethernet MAC
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2014-11-20 16:47:22 -08:00 |
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Florent Kermarrec
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8e4b89849c
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use new direct access on endpoints
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2014-10-20 23:13:37 +08:00 |
|
Florent Kermarrec
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34ed315a48
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remove trailing whitespaces
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2014-10-17 17:14:40 +08:00 |
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Sebastien Bourdeauducq
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e53fb88b85
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uart: minor cleanup and fix
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2014-10-10 15:33:27 +08:00 |
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Florent Kermarrec
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5e5f436aa6
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uart: split it and use dataflow
This make the code easier to understand and allow the reuse of UARTRX & UARTTX
on designs without CPU (e.g miscope).
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2014-10-10 15:24:47 +08:00 |
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Florent Kermarrec
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c0c17030fd
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spi_flash: simplify usage by removing cmd, cmd_width, addr_width parameters
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2014-09-04 15:23:39 +08:00 |
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Sebastien Bourdeauducq
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36434b62f0
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sdram: merge DFII_PIX_RDDATA_SIZE and DFII_PIX_WRDATA_SIZE
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2014-09-03 15:02:38 +08:00 |
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Sebastien Bourdeauducq
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a7b4550e59
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sdramphy/initsequence: cleanup and expose DDR3 MR1 value
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2014-09-03 14:21:30 +08:00 |
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Florent Kermarrec
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114890ee80
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sdramphy/initsequence: clean up mr1/mr2 computation on DDR3 and enable Dynamic ODT
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2014-09-02 10:54:29 +08:00 |
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Sebastien Bourdeauducq
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2234f50223
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k7ddrphy: add bitslip control for incoming DQ
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2014-09-01 19:54:39 +08:00 |
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Sebastien Bourdeauducq
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5483b37c8f
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k7ddrphy: write leveling and read calibration support
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2014-08-31 21:54:28 +08:00 |
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Sebastien Bourdeauducq
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19abe2b888
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k7ddrphy: do not register T at SERDES (fixes timing problem)
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2014-08-31 21:53:35 +08:00 |
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Sebastien Bourdeauducq
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541e5abbc7
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k7ddrphy: update comment
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2014-08-22 19:02:57 +08:00 |
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Sebastien Bourdeauducq
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66fe45ba96
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k7ddrphy: decrease CAS latency to account for cmd/data flight time
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2014-08-22 18:46:01 +08:00 |
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Sebastien Bourdeauducq
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b94647ab16
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k7ddrphy: suppress idiotic bitgen warning about ISERDES IOBDELAY parameter
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2014-08-22 18:45:25 +08:00 |
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Florent Kermarrec
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1c381acc6f
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k7ddrphy: fix read_latency (CL is 2 sys_clk since we use quarter rate)
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2014-08-14 22:46:06 +08:00 |
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Florent Kermarrec
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acbba37f5f
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k7ddrphy: set bitslip to 0 on ISERDESE2 (needed at least for sim)
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2014-08-14 22:46:06 +08:00 |
|
Florent Kermarrec
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2e4bfe154f
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k7ddrphy: add ODELAYE2 on dm path to match dq path (ODELAYE2 even configure with a delay of 0 generates a delay)
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2014-08-14 22:46:06 +08:00 |
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Florent Kermarrec
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bb85f29f91
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k7ddrphy: fix write_latency and take care of OSERDESE2 latency on oe
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2014-08-14 22:46:06 +08:00 |
|
Florent Kermarrec
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85b29c883a
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sdramphy/initsequence: fix and add format_mr0 function
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2014-08-14 14:17:54 +08:00 |
|
Florent Kermarrec
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9844c25df9
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k7ddrphy: add SERDES reset
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2014-08-14 14:16:41 +08:00 |
|
Florent Kermarrec
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194a5a0491
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lasmicon: fix reset_n level
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2014-08-14 14:15:48 +08:00 |
|
Sebastien Bourdeauducq
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c8dd4d2b40
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k7ddrphy: send rddata_valid on all phases
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2014-08-09 11:00:13 +08:00 |
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Sebastien Bourdeauducq
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8deadc5760
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dfii: drive ODT and RESET_N
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2014-08-08 21:56:35 +08:00 |
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Sebastien Bourdeauducq
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1322c0484b
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lasmicon: drive ODT and RESET_N
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2014-08-08 21:55:34 +08:00 |
|
Sebastien Bourdeauducq
|
0550cbb3ce
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lasmicon: add CWL to PHY settings
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2014-08-08 21:55:12 +08:00 |
|
Sebastien Bourdeauducq
|
777ebb7875
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sdramphy/gensdrphy: fix rddata_en generation
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2014-08-08 21:41:07 +08:00 |
|
Sebastien Bourdeauducq
|
a2c7ff4c0c
|
sdramphy: initial K7 DDR3 support
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2014-08-08 21:28:26 +08:00 |
|
Florent Kermarrec
|
293ac09673
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sdramphy/bios: make sdrrd/sdrwr generic
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2014-08-08 19:25:10 +08:00 |
|
Sebastien Bourdeauducq
|
cfc37a3fa5
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sdramphy/initsequence: rewrite DDR3 initialization sequence
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2014-08-08 19:15:05 +08:00 |
|
Sebastien Bourdeauducq
|
e8db842538
|
s6ddrphy: fix DFI interface data width computation
|
2014-08-08 19:14:15 +08:00 |
|
Sebastien Bourdeauducq
|
efb2466c7e
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gensoc: add id for KC705
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2014-08-06 23:53:51 +08:00 |
|
Florent Kermarrec
|
d1ff43faa7
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gensoc/cpuif: do not generate access functions for registers > 64 bits
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2014-08-04 22:38:19 +08:00 |
|
Sebastien Bourdeauducq
|
213cb43ae5
|
Keep only basic SoC designs in MiSoC
|
2014-08-03 12:30:15 +08:00 |
|
Florent Kermarrec
|
25b3aff6f1
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sdramphy: add init sequence for DDR3
|
2014-07-31 10:29:32 +08:00 |
|
Yann Sionneau
|
32171da46d
|
Better UART baudrate generator, and testbench
This enables high speed (tested to 4Mbps) operation.
|
2014-07-31 10:24:52 +08:00 |
|
Florent Kermarrec
|
d4833cb3dc
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cpuif: remove limitations on csr data_width
|
2014-06-28 17:39:55 +02:00 |
Robert Jordens
|
81ed92d3b9
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spiflash: redundant slice
|
2014-05-24 10:39:07 +02:00 |
|
Florent Kermarrec
|
f4c0648289
|
gensdrphy: fix dm generation
|
2014-05-21 21:16:06 +02:00 |
|
Florent Kermarrec
|
54339a6d5b
|
gensdrphy: fix memtype and change phase shift in comments.
|
2014-05-16 16:52:24 +02:00 |
|
Sebastien Bourdeauducq
|
6298624f98
|
sdramphy: remove fixed parameters
|
2014-05-14 16:08:40 +02:00 |
|
Sebastien Bourdeauducq
|
1c08aeb21c
|
Initial mor1kx (OpenRISC) support
Based on milkymist-ng-mor1kx by Stefan Kristiansson
|
2014-05-14 10:24:56 +02:00 |
|
Florent Kermarrec
|
774464155a
|
gensdrphy: clean up and implement data mask
|
2014-05-01 16:17:50 +02:00 |