42d8fc226a
Merge branch 'master' of https://github.com/enjoy-digital/litex
2020-08-23 15:42:39 +02:00
77ae243310
test: add SPDX License identifier to header and specify file is part of LiteX.
2020-08-23 15:40:21 +02:00
b8371ef480
tools: add SPDX License identifier to header and specify file is part of LiteX.
2020-08-23 15:37:16 +02:00
93d906f9d1
soc: add SPDX License identifier and specify file is part of LiteX.
2020-08-23 15:33:01 +02:00
e52ffd2da0
gen: add specify SPDX License identifier and specify file is part of Migen and has been modified/adapted for LiteX.
2020-08-23 15:19:46 +02:00
70610b2332
build: add SPDX License identifier and specify file is part of LiteX.
2020-08-23 15:14:45 +02:00
6ee882d1ec
platforms/targets: add SPDX License identifier to header and specify file is part of LiteX.
2020-08-23 15:08:15 +02:00
ee0e240242
Merge pull request #631 from gsomlo/gls-abc9-fixup
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build/lattice/trellis: make "-abc9" an optional argument
2020-08-22 20:06:57 +02:00
9950e75654
build/io: fix InferedSDRIO (thanks @mtdudek).
2020-08-22 19:49:34 +02:00
bae871a884
Merge pull request #632 from gsomlo/gls-sdcard-refactor
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refactor sdcard (bios) software
2020-08-22 19:44:59 +02:00
3206dba911
Merge pull request #636 from Xiretza/minerva-cli-filetype
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Fix call to generation of minerva output file
2020-08-22 19:41:07 +02:00
8bc5dd7c8c
Merge pull request #635 from Xiretza/collections-abc-deprecation
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Fix DeprecationWarning for collections.abc
2020-08-22 19:40:44 +02:00
7984436248
Merge pull request #634 from betrusted-io/spi_opi_timing_only
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add a pipe register to relax an async_default timing path
2020-08-22 19:39:51 +02:00
e3bb3a9488
Fix call to generation of minerva output file
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With nmigen/nmigen#a7b8ced, cli.py no longer defaults to generating
verilog code, so -t/--type has to be specified explicitly.
$ pytest test/test_targets.py -k test_variants_minerva
[...]
cli.py: error: specify file type explicitly with -t
2020-08-22 14:54:40 +02:00
fcc7058bfc
Fix DeprecationWarning for collections.abc
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DeprecationWarning: Using or importing the ABCs from 'collections' instead of from 'collections.abc' is deprecated since Python 3.3, and in 3.9 it will stop working
2020-08-22 13:39:30 +02:00
d783e86ff6
add a pipe register to relax an async_default timing path
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there is an async reset signal going to a FIFO
that can't be false_path'd because its timing is important
to making sure that the burst FIFO is reset to zero when
a miss happens in the burst cache. Unfortunately as designs
get full, the routability of this signal becomes difficult
and drives up the compile time and reduces quality of results.
There is enough time in the design to insert a single pipe stage
to alleviate the timing somewhat. This commit adds that register.
2020-08-20 04:14:10 +08:00
e0b2b8153f
liblitesdcard/sdcard: read sdcard response only when needed
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Instead of reading the 128 byte sdcard response after each operation,
read it only during debugging and/or when it's necessary (to retrieve
the relative card address, rca).
We no longer need a global sdcard_response array, and refactor the
various retrieval and reporting functions to contain a local buffer
for that purpose, only if/when necessary.
Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
2020-08-17 18:45:24 -04:00
a47b2de5fe
sdcard: refactor command functions
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Factor out common portion of command functions. Also use appropriate
unsigned int width (e.g., uint16_t) for arguments.
Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
2020-08-17 18:45:24 -04:00
bfd6b3c3f4
liblitesdcard/sdcard: cosmetic fixes (indentation, #ifdef, etc.)
2020-08-17 18:45:24 -04:00
37ebcd3be7
factor out busy_wait_us()
2020-08-17 18:45:24 -04:00
c4710b371a
build/lattice/trellis: make "-abc9" an optional argument
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Fix up earlier commit (#6c298cb7) and make the '-abc9' optional
argument to yosys' synth_ecp5 actually optional (and off by default)
in LiteX's trellis build infrastructure.
Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
2020-08-15 16:49:08 -04:00
35929c0f8a
soc/integration/csr_bridge: use registered version only when SDRAM is present.
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Seems to be a good compromise for now.
2020-08-14 15:29:49 +02:00
e4f5dd987e
interconnect/wishbone/Wishbone2CSR: add registered version and use it as default.
2020-08-14 00:47:05 +02:00
b344196aba
build/lattice/diamond: use diamondc instead of pnmainc (avoid having to set environment variables).
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http://www.latticesemi.com/en/Support/AnswerDatabase/5/5/2/5522
2020-08-14 00:10:56 +02:00
f730f1d7ba
cores/cpu/vexriscv_smp fix argument parsing
2020-08-13 12:52:05 +02:00
0e480dd662
bios/main/sdram: fix speed reporting (Mbps/pin not MHz).
2020-08-11 22:13:14 +02:00
bb7f33434e
Merge pull request #627 from gsomlo/gls-dma-addr-64
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RFC: cores/dma, liblitesdcard/sdcard: use 64 bits for dma base address
2020-08-10 21:44:02 +02:00
ba34c85284
cores/dma, liblitesdcard/sdcard: use 64 bits for dma base address
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Make the DMA base address register 64-bit wide, to cover situations
in which the physical memory being accessed is above the 4GB limit
(e.g., on 64-bit systems with more than 4GB of provisioned physical
memory).
Also update DMA reader/writer setup call sites in the bios (currently
only used by litesdcard).
Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
2020-08-10 14:09:25 -04:00
4cf28a0107
software/bios: display SDRAM databits and freq.
2020-08-07 19:49:02 +02:00
6f69679d21
cpu/vexriscv_smp: more coherent_dma to __init__ instead of add_memory_buses.
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LiteX is creating the SoC.dma_bus just after the CPU is declared, so declaring it in add_memory_buses was preventing it.
It's also more coherent to move it to __init__ since not related to the memory_buses.
2020-08-07 14:47:21 +02:00
b3531cd2a8
cores/cpu: add external cpu_type.
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Allows fully pluggable CPUs where cpu_type is set to "external" and cpu_cls provided externally.
2020-08-07 11:16:00 +02:00
b9d3aab59d
targets: use platform.request_all on LedChaser.
2020-08-06 20:02:17 +02:00
14c9166429
build/generic_platform: add request_all method.
2020-08-06 20:00:07 +02:00
57335b9971
cores/cpu/zynq7000: simplify using new loose parameter of Platform.request.
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And avoid the try/except that can mask others errors.
2020-08-06 19:44:46 +02:00
4867f2b324
Merge pull request #624 from trabucayre/emio_zynq
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soc/cores/cpu/zynq7000: add enet0, enet0_mdio, sdio, sdio_cd and sdio_wp only when configured in EMIO mode
2020-08-06 19:34:03 +02:00
48d63f2362
build/generic_plaform: add loose parameter to return None when not available/existing.
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Similar to loose parameter already present on Platform.lookup_request.
2020-08-06 19:33:04 +02:00
81df7b7036
Merge pull request #625 from scanakci/blackparrot_litex
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Blackparrot human name change (IMA), minor transducer fix
2020-08-06 18:50:39 +02:00
188e6f573a
integration/soc/add_etherbone: pass phy to ethcore not self.ethphy.
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Similar in most of the cases but added restrictions.
2020-08-06 18:23:04 +02:00
2457859b2d
update BlackParrot transducer
2020-08-06 12:21:38 -04:00
d2dabcef9a
Blackparrot human name update
2020-08-06 12:21:38 -04:00
87c26a30fd
soc/cores/cpu/zynq7000: add enet0, enet0_mdio, sdio, sdio_cd and sdio_wp only when configured in EMIO mode
2020-08-06 16:45:39 +02:00
d5062d1f4f
Merge pull request #623 from Dolu1990/vexriscv_smp
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cpu/vexriscv_smp Add --with-coherent-dma --without-coherent-dma
2020-08-06 14:31:20 +02:00
07a8e696ce
cpu/vexriscv_smp Add --with-coherent-dma
2020-08-06 13:33:11 +02:00
9a4c5aa1ef
integration/soc/add_sdram: update rules to connect main bus to dram.
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Requires connection when CPU does not have memory buses of when CPU has memory buses
but no DMA bus.
2020-08-05 18:01:12 +02:00
a1644510bf
cpu/vexriscv_smp: fix args_read.
2020-08-05 17:59:30 +02:00
896b68cd6b
cpu/vexriscv_smp: cleanup, fix coherent_dma connection.
2020-08-05 17:25:13 +02:00
342f359e1c
Merge pull request #622 from antmicro/fix_connectors
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arty: Change USB-uart and I2S Pmod configuration
2020-08-05 12:30:34 +02:00
3b293612a8
soc/interconnect/axi: minor cleanups.
2020-08-05 12:11:28 +02:00
303d6cca7e
interconnect/stream: set default AsyncFIFO depth to None and add depth parameter to ClockDomainCrossing.
2020-08-05 12:11:12 +02:00
de9ea19cc7
arty: Change USB-uart and I2S Pmod configuration
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This makes it compatible with the Arty A7 expansion board by Antmicro
(https://github.com/antmicro/arty-expansion-board ).
2020-08-05 11:38:51 +02:00
Florent Kermarrec
Xiretza
bunnie
Gabriel Somlo
Dolu1990
sadullah
Gwenhael Goavec-Merou
Pawel Sagan