Sebastien Bourdeauducq
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261166d92b
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fhdl/verilog: make signal behave as integers in arithmetic (MyHDL style)
See http://jandecaluwe.com/hdldesign/counting.html
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2012-11-29 22:59:54 +01:00 |
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Sebastien Bourdeauducq
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55d143a454
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fhdl/structure: add unary minus
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2012-11-29 22:52:57 +01:00 |
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Sebastien Bourdeauducq
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d8e478efee
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Replace Signal(bits_for(... with Signal(max=...
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2012-11-29 21:53:36 +01:00 |
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Sebastien Bourdeauducq
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50ed73c937
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New specification for width and signedness
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2012-11-29 21:22:38 +01:00 |
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Sebastien Bourdeauducq
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6eebfce44a
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Refactor Case
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2012-11-29 01:11:15 +01:00 |
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Sebastien Bourdeauducq
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070652cc39
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pytholite/reg: use source id in dictionary
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2012-11-29 00:09:35 +01:00 |
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Sebastien Bourdeauducq
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7e2bc00c0a
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Remove Constant
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2012-11-28 23:18:53 +01:00 |
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Sebastien Bourdeauducq
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fee22a4631
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Remove Constant
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2012-11-28 23:18:43 +01:00 |
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Sebastien Bourdeauducq
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79e5f24a65
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Workaround for zero-delay loop simulation problem with Icarus Verilog. TODO: clarify and revert this commit.
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2012-11-28 22:49:22 +01:00 |
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Sebastien Bourdeauducq
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2a3ef28041
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examples/sim/dataflow: update to new APIs
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2012-11-28 22:44:14 +01:00 |
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Sebastien Bourdeauducq
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39d577d65e
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examples/dataflow/dma: update to new APIs
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2012-11-28 22:42:01 +01:00 |
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Sebastien Bourdeauducq
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7c4b5931bc
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examples/basic: remove unroll example
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2012-11-28 22:16:02 +01:00 |
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Sebastien Bourdeauducq
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59831e0485
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fhdl/structure: improved bits_for function
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2012-11-28 18:39:44 +01:00 |
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Sebastien Bourdeauducq
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11b1e53224
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visit/NodeTransformer: copy most nodes
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2012-11-28 17:50:55 +01:00 |
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Sebastien Bourdeauducq
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a2bcbfdf8f
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fhdl/tools: use NodeTransformer to lower arrays
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2012-11-28 17:46:15 +01:00 |
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Sebastien Bourdeauducq
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5440fa715c
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examples/basic/arrays: add array assignment to fragment
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2012-11-26 22:47:35 +01:00 |
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Sebastien Bourdeauducq
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3bc15024ac
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fhdl/tools: use NodeVisitor
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2012-11-26 21:40:23 +01:00 |
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Sebastien Bourdeauducq
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e3a983d731
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Remove unroll
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2012-11-26 20:07:48 +01:00 |
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Sebastien Bourdeauducq
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1460f069f6
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fhdl/structure: remove deprecated MemoryPort
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2012-11-26 19:36:43 +01:00 |
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Sebastien Bourdeauducq
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0620e75cb8
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sram: do not use MemoryPort
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2012-11-26 19:32:56 +01:00 |
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Sebastien Bourdeauducq
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5183774ec8
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bus/wishbone2asmi: do not use MemoryPort
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2012-11-26 19:14:59 +01:00 |
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Sebastien Bourdeauducq
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fc85ca53ad
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actorlib/spi: do not use MemoryPort
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2012-11-26 18:27:59 +01:00 |
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Sebastien Bourdeauducq
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0c29775a8f
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tb/asmicon/asmicon_wb: more complete testing by default
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2012-11-26 18:19:41 +01:00 |
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Sebastien Bourdeauducq
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2418367c7a
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examples/sim/memory: do not use MemoryPort
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2012-11-26 18:19:10 +01:00 |
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Sebastien Bourdeauducq
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dac0d11e52
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actorlib/sim: Dumper
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2012-11-24 00:00:07 +01:00 |
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Sebastien Bourdeauducq
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27d87c9412
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fhdl/structure: disable we_granularity when larger than width
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2012-11-23 23:08:12 +01:00 |
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Sebastien Bourdeauducq
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d2c61e6a90
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sim/generic/multiread: do not return spurious items
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2012-11-23 23:07:25 +01:00 |
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Sebastien Bourdeauducq
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74721b206f
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pytholite: fix import of _Slice
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2012-11-23 21:20:18 +01:00 |
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Sebastien Bourdeauducq
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95122bb778
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pytholite/io: support memory
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2012-11-23 20:36:09 +01:00 |
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Sebastien Bourdeauducq
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f42683b71e
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fhdl/structure/Memory: fix we width
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2012-11-23 19:21:52 +01:00 |
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Sebastien Bourdeauducq
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784a399431
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examples/memory: use new get_port API
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2012-11-23 19:18:08 +01:00 |
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Sebastien Bourdeauducq
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0f6215a13a
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fhdl/structure: add Memory.get_port API
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2012-11-23 19:17:49 +01:00 |
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Sebastien Bourdeauducq
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9d3e218863
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fhdl: use object creation counter (HUID) as hash. This finally makes the generated code textually the same across runs.
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2012-11-23 18:38:03 +01:00 |
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Sebastien Bourdeauducq
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3971600917
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fhdl/structure: use sets for memories and instance collections
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2012-11-23 17:20:08 +01:00 |
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Sebastien Bourdeauducq
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7c6ebcf753
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examples/pytholite/uio: demonstrate memories
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2012-11-23 16:24:20 +01:00 |
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Sebastien Bourdeauducq
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f3efd74dfd
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uio: support memories
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2012-11-23 16:23:24 +01:00 |
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Sebastien Bourdeauducq
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ab31b4d99c
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bus: memory initiator
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2012-11-23 16:22:50 +01:00 |
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Sebastien Bourdeauducq
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0b7dd7bdce
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pytholite/io: fix Wishbone writes + support sel attribute
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2012-11-23 13:40:46 +01:00 |
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Sebastien Bourdeauducq
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20d87682ad
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examples/pytholite/uio: simulate and convert Pytholite
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2012-11-23 13:10:40 +01:00 |
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Sebastien Bourdeauducq
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4c216d8f11
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pytholite/io: support Wishbone reads
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2012-11-23 13:09:55 +01:00 |
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Sebastien Bourdeauducq
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0b24a2ff36
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pytholite/io: support Wishbone writes
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2012-11-23 12:41:50 +01:00 |
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Sebastien Bourdeauducq
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f098c5c695
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pytholite/compiler: pass keyword arguments to gen_io
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2012-11-23 12:40:57 +01:00 |
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Sebastien Bourdeauducq
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51e2e6ecd0
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fhdl/verilog: remove empty cases
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2012-11-18 16:32:51 +01:00 |
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Sebastien Bourdeauducq
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89643bc434
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sim/ipc/Message: convert values
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2012-11-17 23:19:40 +01:00 |
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Sebastien Bourdeauducq
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e92af9de59
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pytholite/transel: use python3-compatible comparison methods
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2012-11-17 23:16:07 +01:00 |
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Sebastien Bourdeauducq
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6434ddd95a
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examples/pytholite: add uio example
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2012-11-17 22:26:14 +01:00 |
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Sebastien Bourdeauducq
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b6b4c5d70e
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uio/ioo: fix UnifiedIOSimulation
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2012-11-17 22:25:42 +01:00 |
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Sebastien Bourdeauducq
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1cabcb3c3f
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uio: support generator trampolining in simulation
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2012-11-17 19:59:22 +01:00 |
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Sebastien Bourdeauducq
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be68ecfc72
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uio: add simulation I/O object
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2012-11-17 19:55:33 +01:00 |
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Sebastien Bourdeauducq
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7add4c6f3c
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uio: unified I/O object
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2012-11-17 19:54:50 +01:00 |