dc087f948a
software/liblitedram/sdram: keep sdrwlon/sdrwloff private.
2020-09-16 11:56:39 +02:00
9c2975e8b4
software/liblitedram/sdram: remove low level manual controls of the DFI interface.
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This was too low level and unused.
2020-09-16 11:22:15 +02:00
8a9d17c768
software/liblitedram/sdram.c: move sdrwl_delays definition to write_leveling section and add #ifdef on reinitialization.
2020-09-16 11:03:10 +02:00
f208a5db2c
Merge pull request #649 from gsomlo/gls-misc-fixup
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misc. fixes for a few recent commits
2020-09-15 21:17:14 +02:00
9729d053eb
software/memtest: use "unsigned long" to represent pointers
2020-09-15 14:46:18 -04:00
6c838cedcd
libbase/sim_debug: wrap markers variables within appropriate #ifdef
2020-09-15 14:46:18 -04:00
e2719d4d71
fixup for e28e808c - don't define variable in .h file
2020-09-15 14:46:18 -04:00
a69273db50
boards/targets/arty: switch SDRAM to NETWORKING mode (interface_type no longer supported).
2020-09-15 19:59:20 +02:00
404104be21
software/liblitedram/sdram.c: increase ddrphy reset time.
2020-09-15 19:58:17 +02:00
cfe6f56572
software/liblitedram/sdram.c: improve reporting.
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- ident sub-reports.
- avoid displaying software/hardware swich if set to previous value.
2020-09-15 19:41:20 +02:00
e63a40370e
software/libbase/memtest: improve reporting.
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- indent sub-reports.
- report speed in MiB/s.
2020-09-15 19:37:09 +02:00
e28e808c24
software/liblitedram: allow forced write leveling delays, improve delay printf when failing.
2020-09-15 19:34:09 +02:00
1d63d66a09
software/libbase/memtest: improve memtest_data progress.
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Add base/current tested address and current/total tested size.
ex:
Memtest at 0x40000000...
Write: 0x40000000-0x40200000 (2/2MiB)
Read: 0x40000000-0x40200000 (2/2MiB)
2020-09-14 11:51:16 +02:00
c169494793
litex_setup: detect and allow execution from a cloned LiteX repository.
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Others dependencies will be installed alongside the Litex repository.
2020-09-10 13:19:34 +02:00
b39fea4ecb
software/liblitedram/write_level_scan: reset write delay even if not succeeding.
2020-09-07 18:53:31 +02:00
658f712001
software/liblitedram/write_level: add support for manual command delay.
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Required on some configurations where automatic cmd/clk scan still has troubles.
2020-09-07 18:47:18 +02:00
5ee074f422
Merge pull request #642 from gsomlo/gls-sdcard-blk-vs-sec
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RFC: bios/sdcard: use (512 byte) blocks as the smallest addressable data unit
2020-09-07 17:41:50 +02:00
c0fb3691e6
Merge pull request #647 from antmicro/jboc/sim-debug
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Improve dynamic tracing support in the simulator
2020-09-07 16:46:37 +02:00
7c3fbf1d06
sim: improve tracing reset value and behaviour with sim_debug=False
2020-09-07 15:29:02 +02:00
3fd567c4c9
sim: additional simulation tracing and debugging tools
2020-09-07 15:28:26 +02:00
c247814ed4
software/liblitedram/sdram.c: add ifdef on MPR functions.
2020-09-05 11:37:07 +02:00
f7b6dd05ae
cores/clock: add initial Xilinx Ultrascale Plus PLL/MMCM/IDELAYCTRL support.
2020-09-03 18:58:10 +02:00
6d8a367abe
software/liblitedram: add separators, expose read_level.
2020-09-03 17:47:32 +02:00
ae152e28a7
software/liblitedram: add sdrmpr functions.
2020-09-03 15:25:04 +02:00
3e083958b0
software/liblitedram: move calibration to sdrcal function.
2020-09-03 14:55:37 +02:00
31afe55821
tools/litex_sim: avoid build/run duplication.
2020-09-03 09:21:37 +02:00
e8f21cd958
build/sim/verilator: cleanup SimVerilatorToolchain, return to initial path after build/run.
2020-09-03 09:21:14 +02:00
d86d20671e
bios/sdcard: use (512 byte) blocks as the smallest addressable data unit
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In liblitesdcard/sdcard.c, replace s/sector/block/ as the 512 byte sized
unit of data transfer to/from the sdcard.
In bios/cmds/cmd_litesdcard.c, do NOT multiply block numbers by 512,
allowing any "block" (a.k.a. "sector") on the sdcard to be addressed for
testing.
Before this patch, user-input "block numbers" were multiplied by 512 and
passed into sdcard_[read|write]() as "sector numbers", with the sdcard
logic internally treating these as 512-byte sized addressable units on
the card. This resulted in only every 512'th 512-byte sized "sector" being
accessible from the bios command line.
Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
2020-09-02 12:07:38 -04:00
222e3f4003
tools/remote/comm_uart: fix offset on write bursts.
2020-09-02 17:23:56 +02:00
6250d4fa41
integration/builder: fix bios_option typo.
2020-09-01 15:39:43 +02:00
267f3e30df
integration/soc/add_spi_flash: update to use new API.
2020-09-01 12:27:43 +02:00
ee6dd5cd20
Merge pull request #644 from Xiretza/sdram-csr-map
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integration/soc: use csr.add() instead of add_csr()
2020-09-01 12:08:33 +02:00
2538b2c300
soc/cores/clock: add with_reset parameter to create_clkout on iCE40PLL/ECP5PLL (similar to others PLLs).
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Avoid instantiating the AsyncResetSynchronizer manually.
2020-09-01 11:50:08 +02:00
f07efcb97f
integration/builder: change bios_options to list and add assert for supported options.
2020-09-01 11:48:52 +02:00
05e8ecf2e2
integration/soc: use csr.add() instead of add_csr()
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add_csr() is defined by SoCCore, so won't work for any instances of
LiteXSoC that aren't also SoCCores. Also, use use_loc_if_exists=True
so SoCCore.csr_map can be used without double allocation errors.
2020-08-31 19:09:49 +02:00
043cfc5df7
soc/interconnect/axi/AXIStreamInterface: manage user as param.
2020-08-31 09:59:05 +02:00
cb8a30944f
Merge pull request #643 from gregdavill/crt0_data_fix
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crt0: fix .data section initialise on [Serv,Minerva]
2020-08-30 19:14:17 +02:00
632cfcc257
soc/cores/cpu/serv: fix crt0 .data initialize
2020-08-30 10:52:16 +09:30
dcd99cc999
soc/cores/cpu/minerva: fix crt0 .data initialize
2020-08-30 10:52:04 +09:30
bda54b1177
software/liblitedram: reset ddrphy before initialization if rst CSR present (added on 7-series).
2020-08-28 17:59:24 +02:00
b44ca6d61a
soc/core/uart: add fixed burst support to UARTBone.
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Allows speeding-up consecutives accesses on the same address. This is currently
used by LiteDRAM bench to speed-up the logging of the BIOS over the crossover UART,
but could be useful for other purposes.
2020-08-28 03:49:50 +02:00
1fb48d308e
soc/cores/uart: add clock domain support to UARTBone.
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In some cases, we want to run UARTBone in a specific clock domain. For example
in LiteDRAM bench, UARTBone is controlling the SoC and the main PLL generating
the sys_clk is reconfigured dynamically, so we want to run UARTBone in a specific
(and fixed) clock domain.
2020-08-28 03:49:45 +02:00
566fbd60c3
cores/uart: minor cleanups on RS232PHYRX/TX.
2020-08-28 03:49:38 +02:00
587e09e3d6
software/liblitesdcard: increase sdcard_wait_cmd_done/sdcard_wait_data_done busy_wait.
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Required after the command refactoring, will need to be adjusted.
2020-08-27 12:52:11 +02:00
4025257d8d
software/liblitesdcard/sdcard: cleanup, update copyrights.
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- improve indent.
- remove do/while in block functions (block's length/count only need to be configured once).
- update copyrights.
2020-08-27 12:36:35 +02:00
334635a97f
software/liblitesdcard: remove wait for DMA Reader to complete, fix ifdef on SDCARD_CMD23_SUPPORT.
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The FIFO after the DMA has been reduced and is no longer able to store an entire block, so the DMA will not complete
if write is not released.
2020-08-26 12:47:50 +02:00
4ac0ed49e1
software/liblitesdcard/bios: add sdfreq command to configure SDCard clock frequency.
2020-08-26 12:43:09 +02:00
3897acb9e4
lattice/nx: update copyrights.
2020-08-24 22:32:49 +02:00
4364043b08
integration/soc: expose integrated_rom_mode to allow ROM to be writable (useful for BIOS/ROM development where content is reloaded over UARTBone/Etherbone).
2020-08-24 18:19:03 +02:00
885c339d97
soc/cores: add initial NX-LRAM support.
2020-08-24 16:24:34 +02:00
Florent Kermarrec
Gabriel Somlo
Jędrzej Boczar
Xiretza
Greg Davill
Piense