Sebastien Bourdeauducq
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2df4ff0ad9
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dvisampler/dma: fix interrupt generation
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2013-05-09 10:51:34 +02:00 |
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Sebastien Bourdeauducq
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d685ed21fc
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dvisampler/dma: bugfixes
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2013-05-08 22:50:40 +02:00 |
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Sebastien Bourdeauducq
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66b4bae7c8
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top: connect dvisampler DMA IRQs
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2013-05-08 22:31:42 +02:00 |
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Sebastien Bourdeauducq
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b3d87e1c79
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software/videomixer: use new DMA engine
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2013-05-08 22:31:18 +02:00 |
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Sebastien Bourdeauducq
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29efa85dec
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dvisampler: new DMA engine (buggy)
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2013-05-08 22:31:01 +02:00 |
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Sebastien Bourdeauducq
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c82b53f1cd
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bank/description/AutoCSR: add autocsr_exclude
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2013-05-08 20:58:57 +02:00 |
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Sebastien Bourdeauducq
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89dbc37ece
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cif: do not generate write function for CSRStatus
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2013-05-08 20:58:27 +02:00 |
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Sebastien Bourdeauducq
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10212e85e7
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dma_asmi: cleanup
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2013-05-08 18:58:50 +02:00 |
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Sebastien Bourdeauducq
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b9b6df6f29
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bank/eventmanager: refactor, rename EventSourceLevel -> EventSourceProcess, add fully externally controlled event source
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2013-05-08 18:12:26 +02:00 |
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Sebastien Bourdeauducq
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8e76c960d9
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timer, uart: EventSourceLevel -> EventSourceProcess
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2013-05-08 18:11:42 +02:00 |
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Sebastien Bourdeauducq
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7a2f31b2e8
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platforms/papilio_pro: no reset signal by default
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2013-05-07 19:10:18 +02:00 |
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Sebastien Bourdeauducq
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439f032921
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crg: support for resetless system clock domain
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2013-05-07 19:09:56 +02:00 |
Florent Kermarrec
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6a4c194aab
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platforms: add KC705
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2013-05-07 10:31:12 +02:00 |
Brandon Hamilton
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3d0894465c
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mibuild: Add platform for Xilinx ML605 board
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2013-05-06 14:21:56 +02:00 |
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Sebastien Bourdeauducq
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e4b0e8ed6d
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xilinx_ise: enable register balancing
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2013-05-06 14:21:39 +02:00 |
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Sebastien Bourdeauducq
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e2d15b169a
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dvisampler: mostly working, very basic and slightly buggy DMA
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2013-05-06 09:58:12 +02:00 |
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Sebastien Bourdeauducq
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f82a16f3a3
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software/videomixer: send to framebuffer
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2013-05-06 09:56:49 +02:00 |
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Sebastien Bourdeauducq
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679d13c99c
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another attempt at fixing clock routing issues
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2013-05-06 09:56:10 +02:00 |
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Sebastien Bourdeauducq
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784e96bb87
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build.py: LOC clock generator components to limit breakage of the ISE shitware
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2013-05-05 23:07:15 +02:00 |
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Sebastien Bourdeauducq
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11cbdf0d4f
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build.py: support single DVI sampler
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2013-05-05 20:56:58 +02:00 |
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Sebastien Bourdeauducq
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d05f3d22e0
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chansync: bugfix
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2013-05-05 15:07:57 +02:00 |
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Sebastien Bourdeauducq
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9c0d13b615
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tb: add chansync
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2013-05-05 15:07:36 +02:00 |
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Sebastien Bourdeauducq
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d175e01876
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dvisampler: connect sync polarity detection
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2013-05-05 12:58:53 +02:00 |
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Sebastien Bourdeauducq
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cb008a061c
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dvisampler/chansync: fix FIFO width
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2013-05-05 12:58:24 +02:00 |
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Sebastien Bourdeauducq
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ad01dc8a74
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software/videomixer: use new resdetection regs
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2013-05-05 11:58:43 +02:00 |
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Sebastien Bourdeauducq
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ea20b74ed1
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dvisampler/resdetection: use DE instead of hsync
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2013-05-05 11:54:36 +02:00 |
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Sebastien Bourdeauducq
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e3e1dcd547
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dvisampler: add sync polarity detection module (thanks Lars for suggestions)
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2013-05-05 11:53:38 +02:00 |
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Sebastien Bourdeauducq
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71e3bba228
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dvisampler/decoding: hold C when DE=1
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2013-05-05 11:51:48 +02:00 |
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Sebastien Bourdeauducq
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4259699d78
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dvisampler: add RawDVISampler
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2013-05-04 20:40:21 +02:00 |
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Sebastien Bourdeauducq
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63073319b0
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dvisampler/datacapture: swap bit pairs
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2013-05-04 20:38:50 +02:00 |
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Sebastien Bourdeauducq
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7a74dae461
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actorlib/spi: add DMAWriteController
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2013-05-04 17:38:54 +02:00 |
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Sebastien Bourdeauducq
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fd089b146f
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actorlib/dma_asmi/OOOWriter: fix tag offset
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2013-05-04 17:38:17 +02:00 |
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Sebastien Bourdeauducq
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53e5c4f59c
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build: only add UCF constraints for the cores that are present
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2013-05-02 23:56:09 +02:00 |
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Sebastien Bourdeauducq
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12deaa91d8
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flow/network/DataFlowGraph: add_buffered_connection
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2013-05-02 13:25:30 +02:00 |
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Sebastien Bourdeauducq
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b5b29f6d5d
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bank/description/CSRStorage: set reset property of storage for use in test benches
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2013-05-02 11:49:23 +02:00 |
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Sebastien Bourdeauducq
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8ffa273719
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flow/network: better determination of plumbing layout
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2013-05-01 22:13:26 +02:00 |
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Sebastien Bourdeauducq
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471393d0f9
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actorlib/dma_asmi: drive dat_wm
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2013-05-01 21:52:26 +02:00 |
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Sebastien Bourdeauducq
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26c0261a4e
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Remove unneeded file
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2013-05-01 17:13:40 +02:00 |
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Sebastien Bourdeauducq
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2e3c2611a6
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software: put network code in a library
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2013-05-01 00:12:13 +02:00 |
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Sebastien Bourdeauducq
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8222ee7f46
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framebuffer: use DMA controller from Migen
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2013-04-30 18:55:35 +02:00 |
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Sebastien Bourdeauducq
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c8810a016f
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actorlib/spi: add DMA read controller
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2013-04-30 18:55:01 +02:00 |
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Sebastien Bourdeauducq
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c70c71502e
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actorlib/spi/SingleGenerator: use CSR alignment bits
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2013-04-30 18:54:47 +02:00 |
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Sebastien Bourdeauducq
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dc0304a87b
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bank/description/CSRStorage: support alignment bits
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2013-04-30 18:53:40 +02:00 |
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Sebastien Bourdeauducq
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51f1ace061
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flow/network/CompositeActor: expose unconnected endpoints
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2013-04-30 18:53:02 +02:00 |
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Sebastien Bourdeauducq
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4f13c5b74d
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flow/network/DataFlowGraph: add add_pipeline
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2013-04-30 15:49:51 +02:00 |
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Sebastien Bourdeauducq
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fb83794ef4
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actorlib/spi/Collector: cleanup, new APIs
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2013-04-28 18:32:46 +02:00 |
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Sebastien Bourdeauducq
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746e452838
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actorlib/dma_asmi: support for writes
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2013-04-28 18:06:36 +02:00 |
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Sebastien Bourdeauducq
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43ac5c8471
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Remove undriven reset signals
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2013-04-25 20:19:49 +02:00 |
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Sebastien Bourdeauducq
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de76faf757
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Tell the Xilinx crapware that DCM_CLKGEN does not phase align, as some (but not all) of the ISE tools remark.
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2013-04-25 20:18:45 +02:00 |
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Sebastien Bourdeauducq
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4ff1175dcf
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Use the Migen asynchronous FIFO
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2013-04-25 19:43:26 +02:00 |