1364ac3657
soc/cores/identifier: append 0 to contents to indicate end of string
2017-06-22 17:53:19 +02:00
bdc61106d1
README: consistency between projects
2017-06-22 17:01:13 +02:00
f720ef5631
soc/tools: simplify litex_server usage and integrage udp, pcie
2017-06-22 11:30:33 +02:00
41a91829eb
soc/tools: syntax fix on comm_pcie, import in __init__.py
2017-06-22 11:29:57 +02:00
c82c1d103f
soc/tools: fix debug prints of comm_pcie
2017-06-22 10:33:08 +02:00
684ae45dbe
soc/tools: remove csr builder from comm_udp (we should use litex_server)
2017-06-22 10:32:39 +02:00
4ea7026747
gen/fhdl/specials: revert migen's commit d98502c6 (specials/Memory: homogenize read-only port syntax) since causing a regression with litepcie
2017-06-10 21:53:53 +02:00
c44a4b051f
soc/interconnect/stream: add first signal to streams (avoid over-complicated code in some cases)
2017-06-09 19:35:48 +02:00
c19c4b711b
soc/cores/identifier: remove additionnal first character
2017-06-08 14:15:27 +02:00
77732fca95
soc/cores/uart: add uart multiplexer
2017-06-05 19:36:30 +02:00
157c2b17bc
boards/platforms/nexys_video: rename hpa to hdp_en on nexy_video hdmi_in port
2017-06-05 15:13:21 +02:00
a36986a501
gen/fhdl/verilog: list available clock domains on keyerror
2017-06-05 14:33:46 +02:00
931ea5ac75
gen/genlib/cdc/gearbox: remove TODO since code is already a good compromise
...
latency can't be reduced that much and reducing ressource usage (already low) would introduce unneeded complexity.
2017-06-01 19:00:22 +02:00
85aea62d74
soc/core: add frequency meter
2017-06-01 00:39:19 +02:00
ff2a9c2176
gen/genlib/cdc/gearbox: add more margin on pointers (for cases where clocks are not perfectly aligned)
2017-05-31 13:23:31 +02:00
4bc6cf6165
soc/cores: dna/xadc: add missing copyright
2017-05-16 21:18:32 +02:00
9350a7b5e6
soc/cores: add dna and xadc (for 7-series, add support for others fpgas?)
2017-05-16 21:02:33 +02:00
6a7604cbb0
Merge pull request #24 from mithro/vivado-mor1k-fix
...
vivado: Fix segfault with or1k.
2017-05-04 15:09:00 +02:00
5f9ff09c08
vivado: Fix segfault with or1k.
...
The or1k doesn't have any verilog include paths added. This means the
code use to generate;
```tcl
synth_design -top top -part xc7a50t-csg325-2 -include_dirs {}
```
which causes Vivado to segfault with the following error;
```
Command: synth_design -top top -part xc7a50t-csg325-2 -include_dirs {}
Starting synth_design
Attempting to get a license for feature 'Synthesis' and/or device 'xc7a50t'
INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7a50t'
Abnormal program termination (11)
Please check 'build/netv2_base_or1k/gateware/hs_err_pid76959.log' for details
Traceback (most recent call last):
File "./make.py", line 82, in <module>
```
2017-04-29 16:44:18 +10:00
bedd428d9d
soc/integration/builder: remove error when compile_software=False and integrated ROM: when using compile_software=False user knows what he's doing.
2017-04-26 13:49:16 +02:00
bb582619eb
gen/genlib/cdc: cleanup lcm computation, fix timeout on BusSynchronizer
2017-04-25 15:13:47 +02:00
e0ce485a17
test/test_gearbox: continue, but we are hitting a simulator bug (related to clock domains declared in modules)
2017-04-25 10:57:34 +02:00
0daeff8689
gen/sim/core: do not use reset_less clock_domains for the one that are created (logic may need to access reset signal)
2017-04-25 10:56:19 +02:00
456cce3ec6
gen/genlib/cdc: import gcd from math and not fractions (deprecated)
2017-04-25 10:55:13 +02:00
3ca0cb0cea
test: add test_gearbox skeleton
2017-04-24 21:41:46 +02:00
b4ebfb4031
test/test_targets: check top.v generation
2017-04-24 19:25:58 +02:00
4c7d460475
litex/gen/util/misc: import gcd from math and not fractions (deprecated)
2017-04-24 19:25:24 +02:00
35e3d93d9b
test: add basic test_targets.py
2017-04-24 19:13:17 +02:00
c0800d25a6
soc/integration/builder.py: don't take care of ROM when compile_software is forced to False
2017-04-24 19:12:30 +02:00
dc66dfcb55
test: add test_bitslip (initially in litedram)
2017-04-24 18:50:06 +02:00
96898f1b39
add test directory with test_code_8b10b.py (from misoc)
2017-04-24 18:46:55 +02:00
b34f74397a
soc/cores: add code_8b10b from misoc
2017-04-19 11:05:21 +02:00
9cfc594280
soc/cores: move flash cores to cores directory
2017-04-19 10:58:15 +02:00
e1319924aa
soc: move uart to a single file
2017-04-19 10:37:59 +02:00
1acca39397
soc/cores: add new spi master, remove obsolete one
2017-04-19 10:22:35 +02:00
f73eb5fe71
gen/genlib/misc: add BitSlip
2017-04-19 09:55:19 +02:00
b708b9cfba
gen/genlib/cdc: add gearbox
2017-04-19 09:54:51 +02:00
e27bc936ef
boards/platforms: add vadj, change user_sw, user_btn IOStandard to LVCMOS25
2017-04-03 17:36:45 +02:00
5efd6a8412
soc/interconnect/stream_packet.py: make error payload optional on Packetizer
2017-03-28 12:21:54 +02:00
d173d946b7
boards/platforms/papilio_pro: fix imports
2017-03-27 10:40:29 +02:00
b6bc040142
boards/platforms/arty: add spi pins
2017-03-20 16:11:00 +01:00
ab075f3d80
Merge pull request #22 from mithro/master
...
soc_core: Add CPU_RESET_ADDR as a constant.
2017-03-12 13:53:27 +01:00
4ee7019852
soc_core: Add CPU_RESET_ADDR as a constant.
...
So we can do a "soft reset" by jumping to this address.
2017-03-12 22:49:36 +11:00
c69012d713
boards/platforms/kcu105: add user_sma_gpio
2017-03-08 16:52:31 +01:00
3f8327bbea
Merge pull request #21 from mithro/master
...
Allow using gcc for or1k.
2017-03-05 11:13:05 +01:00
36bb0f4f3a
Allow using gcc for or1k.
...
* Using CLANG can set by using CLANG=1 or CLANG=0 in the environment.
* or1k continues to default to CLANG if environment is not net.
2017-03-05 19:01:03 +11:00
382b3fb4ca
Merge pull request #20 from cr1901/platforms
...
Add Mercury development board (port from MiSoC)
2017-02-21 14:02:19 +01:00
4dea714ec7
Add Mercury development board (port from MiSoC)
2017-02-21 05:06:51 -05:00
187d9577ab
boards/platforms: fix IOStandard on sfp_tx_disable_n pins
2017-02-20 18:34:49 +01:00
1cda83f11b
build/xilinx/programmer: add target parameter to load_bitstream to select jtag programmer
2017-02-20 17:37:03 +01:00
Florent Kermarrec
Tim 'mithro' Ansell
William D. Jones