Commit Graph

6573 Commits

Author SHA1 Message Date
Florent Kermarrec 3b00a7c4fe README: Add link to the Wiki in the Welcome section. 2021-02-12 13:40:11 +01:00
Florent Kermarrec 041aa9bf6f soc/cores/clock/xilinx_us/USIDELAYCTRL: make sure sys clock domain is reseted when reference clock domain is reseted. 2021-02-09 19:06:49 +01:00
Florent Kermarrec 126dd267d6 soc/interconnect/axi/AXIInterface: add optional tkeep. 2021-02-09 16:27:48 +01:00
enjoy-digital 018094abb2
Merge pull request #809 from stffrdhrn/mor1kx-smp
cpu/mor1kx: Add initial SMP support to cpu core
2021-02-09 09:54:49 +01:00
enjoy-digital 95b310ee0f
Merge pull request #807 from antmicro/revert-bitstream-device-changes
build/xilinx/symbiflow: fix bitstream_device select
2021-02-09 09:26:48 +01:00
enjoy-digital b9bc1d8457
Merge pull request #806 from geertu/bios-improvements
Bios improvements
2021-02-09 09:24:35 +01:00
Stafford Horne 2f2b047f2e cpu/mor1kx: Add initial SMP support to cpu core
In order for mor1kx to run an SMP kernel shadow registers must be
enabled.  This patch adds two new variants:

 - linux+smp - basic linux + smp support
 - linux+smp+fpu - linux with FPU and smp support
2021-02-09 07:06:07 +09:00
Jan Kowalewski ad760d491c build/xilinx/symbiflow: fix bitstream_device select
Signed-off-by: Jan Kowalewski <jkowalewski@antmicro.com>
2021-02-08 15:38:30 +01:00
Geert Uytterhoeven 84e5130ac5 software/bios/console: Call putsnonl() from puts()
puts() and putsnonl() are very similar, and can share code.
Reduce code size by making the former call the latter.

Impact for a RISC-V build:

    $ size console.o.orig console.o
       text	   data	    bss	    dec	    hex	filename
	868	      0	     12	    880	    370	console.o.orig
	832	      0	     12	    844	    34c	console.o

Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>
2021-02-08 14:05:31 +01:00
Geert Uytterhoeven 8e4202ced1 software/bios/readline: Fix warnings if char is signed
When building with --cpu-type=mor1kx:

    litex/soc/software/bios/readline.c: In function 'readline':
    litex/soc/software/bios/readline.c:271:3: warning: case label value exceeds maximum value for type [-Wswitch-outside-range]
      271 |   case KEY_END:
	  |   ^~~~
    litex/soc/software/bios/readline.c:297:3: warning: case label value exceeds maximum value for type [-Wswitch-outside-range]
      297 |   case KEY_DEL:
	  |   ^~~~
    litex/soc/software/bios/readline.c:281:3: warning: case label value exceeds maximum value for type [-Wswitch-outside-range]
      281 |   case DEL:
	  |   ^~~~

The C standard does not specify the signedness of "char", hence this
depends on the implementation.  On e.g. RISC-V, "char" is unsigned, but
on OpenRISC, it is signed.

Fix this by making the "ichar" variable explicitly unsigned.

Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>
2021-02-08 14:05:31 +01:00
Florent Kermarrec 5430c1455e software/demo: add support for absolute/relative --build-path and simplify comment. 2021-02-08 10:29:26 +01:00
enjoy-digital 876ee69e69
Merge pull request #803 from hansfbaier/master
demo: more helpful usage message / support Altera JTAG in litex_term
2021-02-08 10:18:58 +01:00
Florent Kermarrec b485829ec4 MANIFEST.in: update. 2021-02-08 10:11:10 +01:00
Hans Baier 7dae0aa09b litex_term: support Intel/Altera nios2-terminal 2021-02-08 11:42:37 +07:00
Hans Baier 6f63fc104e demo: more helpful usage message 2021-02-06 07:15:12 +07:00
Florent Kermarrec 5cb9f487a2 tools/litex_server: remove JTAGUART's binary_mode parameter (we are now only supporting binary_mode). 2021-02-05 12:38:20 +01:00
Florent Kermarrec 468b916a4f tools/litex_term: add --jtag-config parameter to select OpenOCD JTAG configuration file. 2021-02-05 09:43:32 +01:00
Florent Kermarrec 4f15be746c tools/litex_term: always use binary mode (for jtag_uart and jtagbone) and remove parameter.
Fix jtag_uart regression and allow serialboot.
2021-02-05 09:40:21 +01:00
enjoy-digital 92f4cd1423
Merge pull request #799 from antmicro/add_xc7a200t_to_symbiflow
build/xilinx: add xc7a200t-sbg484-1 to symbiflow toolchain
2021-02-04 16:41:45 +01:00
enjoy-digital 0006efe6ea
Merge pull request #800 from geertu/doc-sphinx-v1-fix
doc: Fix doc build with Sphinx v1.x
2021-02-04 12:24:49 +01:00
Florent Kermarrec 4d1deffbb0 jtagbone/openocd: add binary mode on JTAGUART to fix "\n" to "\r" remapping that is not wanted in binary mode. 2021-02-04 11:44:43 +01:00
Geert Uytterhoeven af13f43e60 doc: Fix doc build with Sphinx v1.x
When building the linux-on-litex-vexriscv documentation with Sphinx
v1.8.5:

    Sphinx error:
    master file linux-on-litex-vexriscv/build/orangecrab/doc/contents.rst not found

The default value of "master_doc" was changed from "contents" to "index"
in Sphinx v2[1].  As the LiteX doc system creates "index.rst", it thus
fails to build with Sphinx v1.x.

Explicitly configure "master_doc" to "index", to make it work with all
versions of Sphinx, regardless of the default.

[1] https://www.sphinx-doc.org/ca/latest/usage/configuration.html?highlight=master_doc

Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>
2021-02-04 09:40:04 +01:00
Jan Kowalewski 57915db746 build/xilinx: add xc7a200t-sbg484-1 to symbiflow toolchain
Signed-off-by: Jan Kowalewski <jkowalewski@antmicro.com>
2021-02-03 15:18:48 +01:00
enjoy-digital b589959084
Merge pull request #796 from antmicro/jboc/gtkwave-savefiles
Fix gtkwave.py to be compatible with python 3.6
2021-02-02 16:30:01 +01:00
Jędrzej Boczar b1fb141d1f Fix gtkwave.py to be compatible with python 3.6 2021-02-02 11:14:16 +01:00
Florent Kermarrec ba7c503fb6 tools/litex_sim: move gtkw import to generate_gtkw_savefile.
This fixes litex_sim use with python 3.6 and raise an error when --gtkwave-savefile
is used with python 3.6.
2021-02-02 10:13:23 +01:00
enjoy-digital 659751d202
Merge pull request #795 from antmicro/jboc/gtkwave-savefiles
Add automatic generator of GTKWave savefiles
2021-02-02 09:59:18 +01:00
enjoy-digital 2f907d6e1e
Merge pull request #790 from antmicro/jboc/8phases
software/liblitedram: support PHYs with more than 4 DFI phases
2021-02-02 09:43:17 +01:00
enjoy-digital d76e0dcede
Merge pull request #791 from antmicro/jboc/init-mr
software/liblitedram: selectable write leveling MR (for LPDDR4 support)
2021-02-02 09:36:31 +01:00
enjoy-digital 4c1dbf9991
Merge pull request #794 from geertu/vexriscv-sbt-failures-are-fatal
cpu/vexriscv_smp: Make sbt failures fatal
2021-02-01 15:16:06 +01:00
Geert Uytterhoeven 7b3737f531 cpu/vexriscv_smp: Make sbt failures fatal
When using a non-default VexRiscv cluster config, the netlist for that
config needs to be generated.  This requires sbt to be installed.
If sbt is missing, an error message is printed:

    sh: 1: sbt: not found

This message may easily be lost in the noise, as the build continues, and fails
later with:

    ERROR: Can't open input file `litex/pythondata-cpu-vexriscv-smp/pythondata_cpu_vexriscv_smp/verilog/VexRiscvLitexSmpCluster_Cc1_Iw32Is4096Iy1_Dw32Ds4096Dy1_Ood_Wm.v' for reading: No such file or directory

Make the root cause more visible by raising an OSError, and aborting the
build.

Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>
2021-02-01 13:54:59 +01:00
Jędrzej Boczar fc9ef4c255 litex_sim: add --gtkwave-savefile argument with example signals 2021-02-01 13:22:30 +01:00
Jędrzej Boczar 01b900f4e0 Add GTKWave savefile generator 2021-02-01 13:22:30 +01:00
Florent Kermarrec 8623536a8a build/generic_platform: avoid removing X pins from named_sc.
We need them on Gowin FPGAs with embedded SDRAM where SDRAM pins are not real IOs.
2021-02-01 13:12:25 +01:00
Florent Kermarrec f324f9531a build/gowin: Don't generate IO_LOC is pin name is X. 2021-02-01 13:08:37 +01:00
enjoy-digital fd33e360fb
Merge pull request #792 from euryecetelecom/master
Add flash method to openFPGALoader class
2021-01-30 21:35:09 +01:00
enjoy-digital 14ce5512a2
Merge pull request #793 from d0ntrash/master
cores/clock/lattice_ice40: add missing AsyncResetSynchronizer import.
2021-01-30 21:34:19 +01:00
Konstantin 3f27253ccc cores/clock/lattice_ice40: add missing AsyncResetSynchronizer import. 2021-01-30 18:25:19 +01:00
Guillaume REMBERT 18a5ace637 Add flash method to openFPGALoader class for support with generic_programmer usage (needed for linux-on-litex-vexriscv) + add offset/address support for firmware load 2021-01-30 13:20:30 +01:00
enjoy-digital 69307cfdde
Merge pull request #789 from antmicro/jboc/litex-sim-fix-name
litex_sim: fix old name: get_cl_cw -> get_default_cl_cwl
2021-01-29 19:13:34 +01:00
Jędrzej Boczar 61e605da92 litex_sim: fix old name: get_cl_cw -> get_default_cl_cwl 2021-01-29 11:31:40 +01:00
Florent Kermarrec 2287f73937 tools/litex_client: add --read/--write args to do simple MMAP accesses to SoC bus.
ex reading/writing to scratch register over jtagbone:

In the SoC:
self.add_jtagbone()

Open LiteX Server:
litex_server --jtag

Do the MMAP accesses:
./litex_cli --read 0x4
0x12345678
./litex_clk --write 0x4 0x5aa55aa5
./litex_cli --read 0x4
0x5aa55aa5
2021-01-28 17:46:18 +01:00
Jędrzej Boczar 38b819c42a software/liblitedram: selectable write leveling MR (for LPDDR4 support) 2021-01-28 15:56:13 +01:00
Jędrzej Boczar e3172faad9 software/liblitedram: support PHYs with more than 4 DFI phases 2021-01-28 15:53:40 +01:00
Florent Kermarrec 7abfbd9825 tools/litex_json2dts/ethernet: add missing 'status = "okay";'.
Was causing https://github.com/litex-hub/linux-on-litex-vexriscv/issues/178.
2021-01-27 11:52:04 +01:00
Florent Kermarrec b8bcbc522f integration/export/triple: use LITEX_ENV_CC_TRIPLE instead of TRIPLE.
triple can be used internally, but is too generic as an environment variable.
2021-01-27 08:25:48 +01:00
enjoy-digital f331ddace8
Merge pull request #780 from garytwong/triple-option
integration/export: allow manually specifying toolchain triple.
2021-01-27 08:16:41 +01:00
Florent Kermarrec 61034fe0f9 litex_setup/update: do a git submodule update --init --recursive on repos with recursive set to True.
Simplify for example pythondata-cpu-vexriscv-smp updates.
2021-01-27 07:55:59 +01:00
Florent Kermarrec 2f89e0aecf soc/do_finalize: check that crg.rst is a Signal before connecting to ctrl._reset. 2021-01-26 17:08:43 +01:00
Florent Kermarrec cafe0944f1 soc/add_uartbone/add_jtagbone: improve phy naming and add uartbone_phy to CSR. 2021-01-26 15:46:55 +01:00