96a265a408
litex_sim: add support for hybrid mac
2020-03-19 10:04:08 +01:00
9e1cd84296
Merge pull request #430 from gsomlo/gls-sdclk-stub
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bios/sdcard: provide sdclk_set_clk() stub for clocker-less targets
2020-03-19 09:05:02 +01:00
b2103f4ad8
bios/sdcard: provide sdclk_set_clk() stub for clocker-less targets
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Targets which lack an adjustable clocker will not expose the required
registers. Provide a stub sdclk_set_clk() routine for those situations.
Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
2020-03-18 15:11:23 -04:00
e865162904
platforms/kcu105: fix pcie tx0 p/n swap.
2020-03-18 19:05:54 +01:00
27720409ce
SPI hardware bitbanging from SD CARD
2020-03-17 09:51:11 +00:00
d45dda731a
SPI hardware bitbanging from SD CARD
2020-03-17 09:50:45 +00:00
50b6db6a6b
SPI hardware bitbanging from SD CARD
2020-03-17 09:50:16 +00:00
2c4b89639f
soc/cores/clock: make sure specific clkoutn_divide_range is only used as a fallback solution.
2020-03-16 11:44:39 +01:00
536ae0e619
Merge pull request #425 from esden/csr-cod-split-reg
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Make CSR documentation diagrams, with more than 8 bits, be split into multiple lanes.
2020-03-14 18:08:24 +08:00
57576fa8fc
Add bit more logic to decide when to switch to multilane CSR documentation.
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Now we only generate multilane bitfield documentation when the CSR has
fields, and the smallest field is less than 8bit long. As this is when
we start running into space problems with the field names.
2020-03-13 14:48:56 -07:00
dda7a8c5f3
Split CSR documentation diagrams with more than 8 bits into multiple lanes.
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In cases when each CSR bit has a name and we use CSR with more than 8
bits, the register diagram quickly becomes crowded and hard to read.
With this patch we split the register into multiple lanes of 8 bits
each.
2020-03-13 14:48:23 -07:00
c0f067c3cf
Merge pull request #427 from enjoy-digital/s7mmcm_fractional_divide
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cores/clock: simplify Fractional Divide support on S7MMCM.
2020-03-13 18:06:23 +01:00
aec1bfbeb4
cores/clock: simplify Fractional Divide support on S7MMCM.
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Specific clkoutn_divide_range can now be provided by specialized XilinxClocking classes.
When provided, the specific range will be used. Floats are also now supported in the
range definition/iteration.
2020-03-13 15:56:39 +01:00
f34593a17d
Merge pull request #421 from betrusted-io/clk0_fractional
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add fractional division options to clk0 config on PLL
2020-03-13 14:15:24 +01:00
eb9f54b2bc
test: add initial (minimal) test for clock abstraction modules.
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Also fix divclk_divide_range on S6DCM.
2020-03-13 12:38:23 +01:00
c304c4db27
targets/icebreaker: add description of the board, link to crowdsupply campagin and to the more complete example.
2020-03-13 09:37:42 +01:00
b5bddc2332
Merge pull request #426 from esden/update-wavedrom
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Updating the vendored wavedrom js files.
2020-03-13 13:44:13 +08:00
d063acb767
Updating the vendored wavedrom js files.
2020-03-12 22:35:04 -07:00
a27385a79c
soc/intergration: rename mr_memory_x parameter to memory_x.
2020-03-12 12:20:48 +01:00
d5da9e0df4
Merge pull request #424 from esden/generate-memory-x
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Add --mr-memory-x parameter to generate memory regions memory.x file
2020-03-12 12:12:48 +01:00
4d02263223
Add --mr-memory-x parameter to generate memory regions memory.x file.
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This file is used by rust embedded target pacs.
2020-03-11 18:12:18 -07:00
e9f0ff68ce
Merge branch 'master' of http://github.com/enjoy-digital/litex
2020-03-11 12:57:29 +01:00
979f98ea31
software: revert LTO changes (Disable it).
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It seems LTO is not yet fully working with all configurations, so it's better
reverting the changes for now.
- cause issues with LM32 available compilers.
- seems to cause issues with min/lite variant of VexRiscv.
- seems to cause issues with some litex-buildenv configurations. (see https://github.com/enjoy-digital/litex/issues/417 ).
2020-03-11 12:57:00 +01:00
01b6969375
Merge pull request #422 from xobs/core-doc-fixes
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Core doc fixes
2020-03-11 19:38:42 +08:00
4ccf62afc1
Merge pull request #423 from gsomlo/gls-ethmac-fixes
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integration/soc: add_ethernet: honor self.map["ethmac"], if present
2020-03-11 12:33:50 +01:00
bb8905fa5d
cores/gpio: add CSR descriptions.
2020-03-11 12:06:15 +01:00
4dabc5a625
cores/icap: add CSR descriptions.
2020-03-11 11:04:42 +01:00
77132a48b0
cores/spi: add CSR descriptions.
2020-03-11 10:58:32 +01:00
6d861c6e57
cores/pwm: add CSR descriptions.
2020-03-11 10:38:28 +01:00
cbc1f5949d
cores/xadc: add CSR descriptions.
2020-03-11 10:05:14 +01:00
a904034811
integration/soc: add_ethernet: honor self.map["ethmac"], if present
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Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
2020-03-10 19:49:34 -04:00
846a2720b7
targets/kcu105: move cd_pll4x.
2020-03-10 17:02:28 +01:00
c97fabb285
targets/kcu105: simplify CRG using USIDELAYCTRL.
2020-03-10 16:48:07 +01:00
3c0b97eec8
cores/clock/USIDELAYCTRL: use separate reset/ready counters and set cd_sys.rst internally.
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This is the behaviour that was duplicated in each target. Integrating it here
will allow simplifying the targets.
2020-03-10 16:46:54 +01:00
a2f61b4e80
soc/cores/spi_opi: documentation fixes
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The ModuleDoc-generated documentation for the spi_opi module produced
slightly invalid output due to ambiguities in how rst assigns headers.
As a result, sections from the spi_opi document would appear as full
sections.
This cleans up these errors so that it parses properly under sphinx.
Signed-off-by: Sean Cross <sean@xobs.io>
2020-03-10 20:40:04 +08:00
d2f6139dc7
soc/cores/i2s: fix rst parsing errors
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The ModuleDoc-generated documentation for the i2s module produced
slightly invalid output due to ambiguities in how rst assigns headers.
As a result, sections from the i2s document would appear as full
sections.
This cleans up these errors so that it parses properly under sphinx.
Signed-off-by: Sean Cross <sean@xobs.io>
2020-03-10 20:37:55 +08:00
bcbf558b6b
bios: add more Ultrascale SDRAM debug with sdram_cdly command to set clk/cmd delay.
2020-03-10 13:08:49 +01:00
5b92bf2d57
add fractional division options to clk0 config on PLL
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S7 MMCMs allow fractional divider on clock 0. Add a fallback
to try fractional values on clock 0 if a solution can't be found.
This is necessary for e.g. generating both a 100MHz and 48MHz
clock from a 12MHz source with margin=0
2020-03-10 18:48:30 +08:00
c4ce6da6c8
Merge pull request #419 from gsomlo/gls-ultra-sdram-fixup
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software/bios: fixup for Ultrascale SDRAM debug
2020-03-10 11:43:23 +01:00
b509068790
cores/clock: add logging to visualize clkin/clkouts and computed config.
2020-03-10 11:13:16 +01:00
04b8a91255
integration/soc: add FPGA device and System clock to logs.
2020-03-10 11:10:23 +01:00
02cba41d64
targets/icebreaker: create CRG after SoC.
2020-03-10 11:09:56 +01:00
4d15e1f7f8
software/bios: fixup for Ultrascale SDRAM debug
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Keep CSR accesses independent of csr_data_width and csr_alignment.
Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
2020-03-09 15:32:08 -04:00
ba2f31d43d
integration/soc: set use_rom when cpu_reset_address is defined in a rom region.
2020-03-09 19:36:47 +01:00
8808c884c5
boards/platforms/icebreaker: cleanup a bit.
2020-03-09 19:16:02 +01:00
4656b1b2ad
software/common: fix LTO checks.
2020-03-09 19:08:27 +01:00
2a91deadcb
soc/cores/clock/iCE40PLL: add SB_PLL40_PAD support.
2020-03-09 19:03:05 +01:00
38d7f8a6e6
build/lattice/icestorm: add timingstrict parameter and default to False. (similar behavior than others backends)
2020-03-09 19:02:23 +01:00
1e9aa64387
targets/icebreaker: simplify, use standard VexRiscv, add iCE40PLL and run BIOS from SPI Flash.
2020-03-09 19:01:16 +01:00
197bdcb026
lattice/icestorm: enable DSP inference with Yosys and avoid setting SPI Flash in deep sleep mode after configuration which prevent running ROM CPU code from SPI Flash.
2020-03-09 16:51:18 +01:00
Piotr Binkowski
enjoy-digital
Gabriel Somlo
rob-ng15
Sean Cross
Piotr Esden-Tempski
bunnie