fb0c9e846d
build/add_period_constraint: Simplify by using new integrated cases in generic add_period_constraint.
2023-05-17 16:45:45 +02:00
c40963531c
build/generic_platform build/xxx/platform soc/integration/builder:
...
generic_platform add a method to return extension for sram/flash
vendor platform: bitstream_ext -> _bitstream_ext and replace by a dict
when extension depends on mode
builder: use `get_bitstream_extension` instead of directly using
bitstream_ext
2023-03-04 11:36:29 +01:00
d061e9b9cf
build/xxx/platform: adding methods to return toolchains list by device, and args by toolchain
2022-11-06 11:22:32 +01:00
af445e93dd
build/vendor/common: Minor style cleanup.
2022-10-24 09:33:35 +02:00
2fba07daf8
build/gowin: Use build_name instead of top for generated files.
2022-08-05 08:30:34 +02:00
3c1e8e74fc
build: Cosmetic cleanups.
2022-08-05 08:22:36 +02:00
7789e1875a
build/gowin: Fix build regression (build_name -> self._build_name).
2022-07-26 09:59:20 +02:00
eb0f00f295
build/generic_toolchain: _build -> build. All toolchains: override build only when required
2022-07-03 22:12:43 +02:00
6541a6c93b
build: gowin lattice/diamond lattice/oxide lattice/radiant microsemi quicklogic move to GenericToolchain
2022-06-26 21:40:56 +02:00
3e10576fcd
build/gowin: Fix bitstream copy to gateware directory.
2022-06-15 21:45:19 -04:00
2ec0ebe40f
build/gowin: Add copy of bitstream to from impl to gateware directory.
2022-03-17 09:35:34 +01:00
7411109f4d
gowin/programmer: Fix copyright year.
2022-03-08 17:25:27 +01:00
700077e4a1
powershell and WSL support
2022-03-08 13:52:03 +08:00
cfab857c7b
win/powershell support.
...
add gowin programmer support.
2022-03-08 13:16:01 +08:00
419d605e38
build/toolchains: Specify passed toolchain when unknown.
2022-01-26 11:56:22 +01:00
b7b054d48e
gowin: add hack for copackaged PSRAM
...
Some Gowin FPGAs has copackaged "PSRAM" instead of "HyperRAM". They're
in fact also HyperRAM, but named differently and because of this needs
slightly changed hack.
Add hack for PSRAM too. In case of two PSRAM chips are used, the bus is
wider so the needed definition is already in place, so the bus width
hack is not needed.
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
2022-01-23 03:08:18 +08:00
49d8000d49
gowin/common: Add Differential Input/Output support.
2021-09-20 14:14:06 +02:00
9c373242af
gowin: Add HyperRAM integration hack to match Gowin EDA expected pattern.
2021-09-20 11:47:32 +02:00
730b57d9cd
build/gowin: Add initial timing constraints support.
2021-07-15 11:06:03 +02:00
2b393254da
build: Simplify attr_translate (Now automatically defaults to None when not explicitely listed).
...
Most of the attributes are Xilinx specific, it does not make sense to provide them on other FPGA devices.
2021-07-15 09:59:15 +02:00
4fd974be10
build/gowin: Minor cleanups.
2021-07-15 09:36:41 +02:00
6fc87f7c85
build/gowin/common: Add DDRInput/DDROutput implementations.
2021-07-14 10:01:54 +02:00
cfbc06c297
build/gowin/common: Add AsyncResetSynchronizer implementation.
2021-07-14 09:37:00 +02:00
f324f9531a
build/gowin: Don't generate IO_LOC is pin name is X.
2021-02-01 13:08:37 +01:00
db836e8e5d
build: add toolchain check before running build script and improve error reporting.
2020-11-04 09:42:18 +01:00
eca5a25e27
add dummy attr_translate
2020-09-29 15:55:07 +02:00
dd2b1f21f0
typo and dead code
2020-09-29 15:24:36 +02:00
95564b7475
change name->devicename, working bios
2020-09-28 17:49:41 +02:00
c0fa4fd1f4
initial build support for Gowin
2020-09-28 13:12:07 +02:00
Florent Kermarrec
Gwenhael Goavec-Merou
William D. Jones
curliph
Icenowy Zheng
Pepijn de Vos