Commit graph

982 commits

Author SHA1 Message Date
Sebastien Bourdeauducq
548f2685bb platform/rhino: rename ismm data out signal to locked 2013-05-30 11:06:02 +02:00
Sebastien Bourdeauducq
bac62a32a9 Make memory ports part of specials
This is needed to handle cases where a single memory has ports
in two different modules, and one of these modules is subject
to clock domain remapping. The clock domain of the port in that
module only must be remapped.
2013-05-28 16:11:34 +02:00
Sebastien Bourdeauducq
759858f739 Use migen.fhdl.std 2013-05-26 18:07:26 +02:00
Sebastien Bourdeauducq
c13e573e9f Require Python 3.3 2013-05-26 18:02:18 +02:00
Sebastien Bourdeauducq
70ffe86356 New migen.fhdl.std to simplify imports + len->flen 2013-05-22 17:11:09 +02:00
Sebastien Bourdeauducq
5208baada8 bus/wishbone/SRAM: support init and read_only 2013-05-19 20:53:54 +02:00
Sebastien Bourdeauducq
7ada0159fd bus/csr/SRAM: support init 2013-05-19 20:53:37 +02:00
Sebastien Bourdeauducq
e272e68fac platforms/papilio_pro: swap tx/rx to be consistent with M1 2013-05-19 20:24:47 +02:00
Sebastien Bourdeauducq
27accd72b5 setup.py: update required Python version 2013-05-16 15:24:11 +02:00
Sebastien Bourdeauducq
fe64ade1ac platforms/m1: add pots pins 2013-05-13 15:38:20 +02:00
Sebastien Bourdeauducq
792b8fed1b bus/asmi: port sharing support 2013-05-12 15:58:39 +02:00
Sebastien Bourdeauducq
f202946717 fhdl/tools/_TargetLister: do not include array keys in targets 2013-05-11 17:28:41 +02:00
Sebastien Bourdeauducq
0ec6a7eb4e genlib/record: match_by_position -> connect_flat 2013-05-11 11:48:21 +02:00
Sebastien Bourdeauducq
955a9733c8 Revert "genlib/record/connect: add match_by_position"
This reverts commit df1ed32765.
2013-05-10 17:41:51 +02:00
Sebastien Bourdeauducq
c82b53f1cd bank/description/AutoCSR: add autocsr_exclude 2013-05-08 20:58:57 +02:00
Sebastien Bourdeauducq
10212e85e7 dma_asmi: cleanup 2013-05-08 18:58:50 +02:00
Sebastien Bourdeauducq
b9b6df6f29 bank/eventmanager: refactor, rename EventSourceLevel -> EventSourceProcess, add fully externally controlled event source 2013-05-08 18:12:26 +02:00
Sebastien Bourdeauducq
7a2f31b2e8 platforms/papilio_pro: no reset signal by default 2013-05-07 19:10:18 +02:00
Sebastien Bourdeauducq
439f032921 crg: support for resetless system clock domain 2013-05-07 19:09:56 +02:00
Florent Kermarrec
6a4c194aab platforms: add KC705 2013-05-07 10:31:12 +02:00
Brandon Hamilton
3d0894465c mibuild: Add platform for Xilinx ML605 board 2013-05-06 14:21:56 +02:00
Sebastien Bourdeauducq
e4b0e8ed6d xilinx_ise: enable register balancing 2013-05-06 14:21:39 +02:00
Sebastien Bourdeauducq
7a74dae461 actorlib/spi: add DMAWriteController 2013-05-04 17:38:54 +02:00
Sebastien Bourdeauducq
fd089b146f actorlib/dma_asmi/OOOWriter: fix tag offset 2013-05-04 17:38:17 +02:00
Sebastien Bourdeauducq
12deaa91d8 flow/network/DataFlowGraph: add_buffered_connection 2013-05-02 13:25:30 +02:00
Sebastien Bourdeauducq
b5b29f6d5d bank/description/CSRStorage: set reset property of storage for use in test benches 2013-05-02 11:49:23 +02:00
Sebastien Bourdeauducq
8ffa273719 flow/network: better determination of plumbing layout 2013-05-01 22:13:26 +02:00
Sebastien Bourdeauducq
471393d0f9 actorlib/dma_asmi: drive dat_wm 2013-05-01 21:52:26 +02:00
Sebastien Bourdeauducq
c8810a016f actorlib/spi: add DMA read controller 2013-04-30 18:55:01 +02:00
Sebastien Bourdeauducq
c70c71502e actorlib/spi/SingleGenerator: use CSR alignment bits 2013-04-30 18:54:47 +02:00
Sebastien Bourdeauducq
dc0304a87b bank/description/CSRStorage: support alignment bits 2013-04-30 18:53:40 +02:00
Sebastien Bourdeauducq
51f1ace061 flow/network/CompositeActor: expose unconnected endpoints 2013-04-30 18:53:02 +02:00
Sebastien Bourdeauducq
4f13c5b74d flow/network/DataFlowGraph: add add_pipeline 2013-04-30 15:49:51 +02:00
Sebastien Bourdeauducq
fb83794ef4 actorlib/spi/Collector: cleanup, new APIs 2013-04-28 18:32:46 +02:00
Sebastien Bourdeauducq
746e452838 actorlib/dma_asmi: support for writes 2013-04-28 18:06:36 +02:00
Sebastien Bourdeauducq
85e06cc100 xilinx_ise: implement NoRetiming synthesis constraint 2013-04-25 14:57:45 +02:00
Sebastien Bourdeauducq
e97edd7253 genlib/fifo: disable retiming on Gray counter outputs 2013-04-25 14:57:07 +02:00
Sebastien Bourdeauducq
156ef43ace genlib/cdc: add NoRetiming 2013-04-25 14:56:45 +02:00
Sebastien Bourdeauducq
b862b070d6 fhdl/verilog: recursive Special lowering 2013-04-25 14:56:26 +02:00
Sebastien Bourdeauducq
67c3119249 genlib/fifo: add asynchronous FIFO 2013-04-25 13:30:37 +02:00
Sebastien Bourdeauducq
fee228a09f fhdl/specials/memory: do not write address register for async reads 2013-04-25 13:30:05 +02:00
Sebastien Bourdeauducq
6c08cd67aa graycounter: expose binary output 2013-04-25 13:11:15 +02:00
Sebastien Bourdeauducq
0f9df2d732 genlib: add Gray counter 2013-04-24 19:13:36 +02:00
Florent Kermarrec
f599fe4ade Support for resetless clock domains 2013-04-23 11:54:05 +02:00
Sebastien Bourdeauducq
bd0ae6592e Add setup.py 2013-04-19 14:04:59 +02:00
Sebastien Bourdeauducq
6204bcfa10 README: fix quick intro 2013-04-19 14:00:46 +02:00
Sebastien Bourdeauducq
29eaf068f3 xilinx_ise: do not attempt to source settings file on Windows 2013-04-16 22:55:24 +02:00
Sebastien Bourdeauducq
31b1960188 xilinx_ise: add --no-source option to disable sourcing of ISE settings file 2013-04-16 22:39:35 +02:00
Sebastien Bourdeauducq
ceb0a99d83 Change license to 2-clause BSD 2013-04-15 23:55:30 +02:00
Sebastien Bourdeauducq
8e11fcf1d0 bus/csr/SRAM: fix Module conversion errors 2013-04-14 13:55:04 +02:00