Florent Kermarrec
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f7b6dd05ae
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cores/clock: add initial Xilinx Ultrascale Plus PLL/MMCM/IDELAYCTRL support.
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2020-09-03 18:58:10 +02:00 |
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Florent Kermarrec
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77ae243310
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test: add SPDX License identifier to header and specify file is part of LiteX.
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2020-08-23 15:40:21 +02:00 |
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Florent Kermarrec
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383fcd36d6
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soc/cores/clock: add CycloneVPLL.
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2020-04-07 17:24:12 +02:00 |
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Florent Kermarrec
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0f17547c5b
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soc/cores/clock: add initial AlteraClocking/CycloneIV support.
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2020-04-07 16:59:53 +02:00 |
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Florent Kermarrec
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eb9f54b2bc
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test: add initial (minimal) test for clock abstraction modules.
Also fix divclk_divide_range on S6DCM.
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2020-03-13 12:38:23 +01:00 |