Hardware
/
litex
mirror of https://github.com/enjoy-digital/litex.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity
9,847 Commits 40 Branches 14 Tags 51 MiB
Commit Graph

9847 Commits

Author SHA1 Message Date
Meinhard Kissich 12b9c8b2e7 cpu/fazyrv: Fix minor path typo 2024-03-04 21:44:18 +01:00
Gwenhael Goavec-Merou 044760e06c build/colognechip/colognechip: check if p_r is in PATH before trying to copy dly file 2024-03-02 12:23:10 +01:00
Florent Kermarrec 62f275debd cpu/fazyrv: Expose parameters and fix vdir. 
On your targets: --cpu-type=fazyrv --help:

CPU options.:
  --cpu-chunksize {1,2,4,8}
          Size of the chunks, i.e., the data path. (default: 8)
  --cpu-conf {MIN,INT,CSR}
          Configuration of the processor. (default: MIN)
  --cpu-rftype {LOGIC,BRAM,BRAM_BP,BRAM_DP,BRAM_DP_BP}
          Implementation of the register file. (default: BRAM_DP_BP)

Then: litex_sim --cpu-type=fazyrv --cpu-chunksize=4 --cpu-rftype=LOGIC

        __   _ __      _  __
       / /  (_) /____ | |/_/
      / /__/ / __/ -_)>  <
     /____/_/\__/\__/_/|_|
   Build your hardware, easily!

 (c) Copyright 2012-2024 Enjoy-Digital
 (c) Copyright 2007-2015 M-Labs

 BIOS built on Mar  1 2024 10:49:12
 BIOS CRC passed (a3cd3faa)

 LiteX git sha1: 45835b4b

--=============== SoC ==================--
CPU:		FazyRV-STANDARD @ 1MHz
BUS:		wishbone 32-bit @ 4GiB
CSR:		32-bit data
ROM:		128.0KiB
SRAM:		8.0KiB


--============== Boot ==================--
Booting from serial...
Press Q or ESC to abort boot completely.
sL5DdSMmkekro
Timeout
No boot medium found

--============= Console ================--

litex>
 2024-03-01 10:49:37 +01:00
Gwenhael Goavec-Merou 45835b4b9d build/colognechip/colognechip: workaround for p_r complaining about a missing dly file (will be fixed by the next CologneChip's toolchain release) 2024-03-01 07:12:11 +01:00
Florent Kermarrec 697fb51a32 soc/cores/cpu: Add initial FazyRV support with default variant. 
It will then be useful to expose the different parameters or create variants.

litex_sim --cpu-type=fazyrv:

        __   _ __      _  __
       / /  (_) /____ | |/_/
      / /__/ / __/ -_)>  <
     /____/_/\__/\__/_/|_|
   Build your hardware, easily!

 (c) Copyright 2012-2024 Enjoy-Digital
 (c) Copyright 2007-2015 M-Labs

 BIOS built on Mar  1 2024 06:49:55
 BIOS CRC passed (1ee1fd74)

 LiteX git sha1: 4ca66bbe

--=============== SoC ==================--
CPU:		FazyRV-STANDARD @ 1MHz
BUS:		wishbone 32-bit @ 4GiB
CSR:		32-bit data
ROM:		128.0KiB
SRAM:		8.0KiB


--============== Boot ==================--
Booting from serial...
Press Q or ESC to abort boot completely.
sL5DdSMmkekro
Timeout
No boot medium found

--============= Console ================--

litex>
 2024-03-01 06:52:02 +01:00
inc eeeffa9ffd support TQFP144 ECP5 package 2024-02-29 21:30:25 +01:00
Florent Kermarrec 4ca66bbee6 interconnect/wishbone/Remapper: Fix src_adr/dst_adr signal size. 2024-02-28 19:11:59 +01:00
Florent Kermarrec 722b6da9fb test/test_wishbone: Improve origin_region_remap_test to test more complex remapping. 2024-02-28 19:11:55 +01:00
Gwenhael Goavec-Merou 3d9db91387 build/colognechip/colognechip: add missing p_r option (-cCP) 2024-02-28 17:17:42 +01:00
Gwenhael Goavec-Merou 83c1adbc94 soc/cores/clock/colognechip: set lock_req to 1 by default and connect locked to USR_PLL_LOCKED_STDY 2024-02-28 17:17:06 +01:00
Gwenhael Goavec-Merou 54d19265a7 build/colognechip/platform: typo bitstream_ext -> _bitstream_ext 2024-02-28 16:12:30 +01:00
Gwenhael Goavec-Merou 8eb5e7b6c1 soc/cores/clock/colognechip: REF_CLK/OUT_CLK: int -> str 2024-02-28 16:11:27 +01:00
Florent Kermarrec cd8ad3714d soc/interconnect/packet/Dispatcher: Add missing **kwargs. 2024-02-28 13:32:09 +01:00
Florent Kermarrec 42c1046323 soc/interconnect/packet: Add **kwargs to Arbiter/Dispatcher to allow specifying keep/omit parameters for connection. 2024-02-28 13:04:48 +01:00
Florent Kermarrec fea3a7ebc6 cpu/naxriscv/core/git_setup: Clone submodules as recursive to prevent errors with submodules during the git checkout. 2024-02-27 15:59:44 +01:00
Florent Kermarrec 253d1cfb9b build/generic_platform/ConstraintManager: Add prepend parameter to add_extension. 
In some cases, prepend is useful when we want to replace existing IOs.
 2024-02-26 17:28:03 +01:00
Florent Kermarrec d3ea912339 CHANGES: Update. 2024-02-22 10:24:35 +01:00
enjoy-digital 7f91baae3a
Merge pull request #1894 from mdejw/patch-1 
Send serial data to sim uart only if rx_ready is set.
 2024-02-22 10:22:05 +01:00
enjoy-digital dc229f8df9
Merge pull request #1895 from trabucayre/json2dts_linux_fill_network 
tools/litex_json2dts_linux.py: adding ip= bootarg when localip and remoteip are provided
 2024-02-22 10:20:41 +01:00
Gwenhael Goavec-Merou a6d015a358 tools/litex_json2dts_linux.py: adding ip= bootarg when localip and remoteip are provided 
Signed-off-by: Gwenhael Goavec-Merou <gwenhael@enjoy-digital.fr>
 2024-02-22 09:40:26 +01:00
Marcin Dawidowicz 0de87ce40d
Send serial data to sim uart only if rx_ready is set. 2024-02-21 22:32:49 +01:00
Florent Kermarrec 63f9935f17 build/sim/config: Convert periods_ps to int since otherwise too restrictive on possible frequencies generation. 2024-02-21 11:39:49 +01:00
Florent Kermarrec 129446dea2 test/test_wishbone: Run all Remapper tests in byte and word modes and simplify. 2024-02-21 11:20:01 +01:00
Florent Kermarrec c1dad9516a interconnect/wishbone/Remapper: Shift origin when in word mode, fixes unit-test. 2024-02-21 11:06:15 +01:00
Florent Kermarrec 6213fd2151 test/test_wishbone: Add Remapper unit-test for word addressing mode. 2024-02-21 11:05:35 +01:00
Florent Kermarrec c0517cd1cf interconnect/axi: Use same default parameters than wishbone.Remapper. 2024-02-20 16:58:37 +01:00
Florent Kermarrec d1e73889f9 test/test_wishbone: Add wishbone.Remapper basic tests. 2024-02-20 16:51:32 +01:00
Florent Kermarrec ef256c9cc2 interconnect/wishbone: Enhance Remapper to also integrate RegionsRemapper functionnality and apply operation sequentially. 2024-02-20 16:50:56 +01:00
Florent Kermarrec d78dbd6935 soc/add_spi_flash: Revert PHY_FREQUENCY definition and use in BIOS. 2024-02-20 14:23:54 +01:00
Gwenhael Goavec-Merou 03340bcf12 soc/software/liblitespi/spiflash: replace SPIFLASH_PHY_FREQUENCY by CONFIG_CLOCK_FREQUENCY (removed by commit e498a56698) 2024-02-19 06:34:26 +01:00
enjoy-digital 677443cef7
Merge pull request #1890 from rtucker85/fix_csr_merge 
Fixes for errors when attempting import of Sub-SoCs .json
 2024-02-16 18:27:39 +01:00
Richard Tucker 6c8633b9a3 soc/integration/builder: add_json: fix order of parameters 
For consistancy only. This now matches load_csr_json.

Link: https://git.motec.com.au/id/Ibe2889fafc6ef48a6f217f84246de11a9555811d
 2024-02-16 16:59:14 +11:00
Richard Tucker d4c1c97cf9 soc/integration/export: fix incorrect element in get_linker_regions 2024-02-16 15:38:48 +11:00
Florent Kermarrec cfbe3b028a interconnect/wishbone/RegionsRemapper: Add default values for src_regions/dst_regions. 2024-02-13 19:13:00 +01:00
Florent Kermarrec 595118fd5d interconnect/wishbone/RegionsRemapper: Connect adr by default when no remapping. 2024-02-13 18:31:05 +01:00
Florent Kermarrec 5ee746f178 interconnect/wishbone: Add initial RegionsRemapper to allow remapping source regions to destination regions. 2024-02-13 18:25:46 +01:00
Florent Kermarrec 19db80ec9b interconnect/Remapper: Add docstring description. 2024-02-13 17:44:02 +01:00
Florent Kermarrec fe0363da25 CHANGES.md: Update. 2024-02-13 16:04:13 +01:00
Florent Kermarrec bd7921cda8 soc/add_master: Add region support to allow remapping. 
Allow connecting a master to a specific region of the SoC and limiting access to it.
 2024-02-13 15:59:42 +01:00
Florent Kermarrec 36767c66b4 soc/SoCRegion: Ensure fixed indentation in __str__. 2024-02-13 14:52:29 +01:00
enjoy-digital 46a2e6fe78
Merge pull request #1887 from Dolu1990/jtag 
tools/litex_sim support for remote_bitbang (openocd)
 2024-02-13 14:29:11 +01:00
enjoy-digital 89bf0fb0cf
Merge pull request #1888 from Dolu1990/reset_vector 
core/vexriscv_smp add reset vector support
 2024-02-13 11:43:40 +01:00
Dolu1990 795fa1e1fc core/vexriscv_smp add reset vector support 2024-02-13 11:22:05 +01:00
Dolu1990 0a315cda2d Merge branch 'master' into jtag 
# Conflicts:
#	litex/soc/cores/cpu/vexriscv_smp/core.py
 2024-02-13 10:41:26 +01:00
Dolu1990 fe37dcf6dd tools/litex_sim now support remote_bitbang (openocd) 
soc/cores/vexriscv_smp add jtag tap support
 2024-02-13 10:35:53 +01:00
Florent Kermarrec f36e7d379a CHANGES.md: Update. 2024-02-12 17:21:42 +01:00
Florent Kermarrec 244bc43886 soc/integration/builder: Add add_json method to allow adding exported .json from Sub-SoCs. 
Ex: builder.add_json("icebreaker_soc.json", 0x30000000, "icebreaker_soc") to import/merge
a SoC's json file from a Sub-SoC in Main-SoC.
 2024-02-12 17:19:04 +01:00
Florent Kermarrec 38ff48a543 soc/integration/export: Add load_csr_json function to load/import .json exports. 
Useful to merge SoC/Sub-SoCs Constants/CSRs/Memory Regions.
 2024-02-12 17:16:54 +01:00
Florent Kermarrec 1b32d8a341 soc/add_etherbone: Revert sys_clk domain renaming when ethmac is disabled. 2024-02-09 15:10:47 +01:00
Florent Kermarrec afcf78f643 soc/add_etherbone: Rename ethmac parameters with ethmac suffix since related to ethmac. 2024-02-07 19:21:38 +01:00