d6eeb20505
tools/litex_term: Minor cosmetic changes.
2024-04-18 15:09:24 +02:00
22f4637570
Revert "Uart tx irq handling fix " (issue #554 )
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This reverts commit 6885770e47
2024-04-16 14:01:38 +02:00
3978af9c39
test/test_hyperbus: Update.
2024-04-16 11:12:30 +02:00
a44b7944ca
CHANGES: Update.
2024-04-16 10:51:19 +02:00
fd6f913525
cores/hyperbus: Switch default latency_mode to variable.
2024-04-16 10:20:18 +02:00
62b9c64212
cores/hyperbus: Add status register to report configured latency_mode to software and allow corresponding configuration.
2024-04-16 10:18:53 +02:00
576ab24b6c
Merge pull request #1926 from enjoy-digital/hyperbus_variable_latency
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HyperRAM: Add variable latency and configuration support.
2024-04-15 17:39:04 +02:00
e3d1391487
Merge pull request #1925 from chmousset/fix_efinix_t8q144
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[fix] T8Q144 PLL input instance reference
2024-04-15 17:38:37 +02:00
ebabe82c70
software/bios/main: Rewrite HyperRAM init/config.
2024-04-15 16:03:55 +02:00
67586e8a24
cores/hyperbus: Update docstring.
2024-04-15 15:05:58 +02:00
d25fd85f55
cores/hyperbus: More cleanups.
2024-04-15 14:56:08 +02:00
2100a6bd8c
cores/hyperbus: reg_buf.source -> reg_ep.
2024-04-15 14:48:38 +02:00
1597791fb6
cores/hyperbus: Simplify reg_write/read_done.
2024-04-15 14:43:15 +02:00
8e48d0d330
cores/hyperbus: Cleanup/Improve Config/Reg Interfaces.
2024-04-15 14:33:41 +02:00
6e00cfa9d0
cores/hyperbus: Cleanup fixed/variable latency support.
2024-04-15 14:05:39 +02:00
739b66a15b
[fix] Trion T8 have a V1 PLL in BGA packages, but a V2 PLL in TQFP package. DP files varies accordingly
2024-04-15 12:09:18 +02:00
93f76ede95
bios/main: Test down to latency = 3, working.
2024-04-15 12:06:49 +02:00
a95f1b8486
cores/hyperbus: Make latency dynamically configurable.
2024-04-15 12:06:11 +02:00
6216bd4e99
cores/hyperbus: Add latency_mode parameter and test different latencies/modes in simulation.
2024-04-15 10:32:13 +02:00
33a1fcda48
software/bios: Do minimal reconfiguration for variable latency and start testing latency cycles re-configuration.
2024-04-12 19:35:31 +02:00
f8c59c03e3
cores/hyperbus: Add variable latency support (working on ti60 f225).
2024-04-12 18:50:19 +02:00
b192103822
cores/hyperbus: Fix bytes order on register writes.
2024-04-12 16:06:26 +02:00
fb519ac260
test/test_hyperbus: Add test_hyperram_reg_write.
2024-04-12 15:21:57 +02:00
a32db7abad
cores/hyperbus: Add with_csr parameter to make Register interface optional.
2024-04-12 15:21:32 +02:00
2d1dd45fd2
Merge pull request #1919 from nrndda/uart_tx_irq_handling_fix
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Uart tx irq handling fix
2024-04-12 10:45:12 +02:00
2bc41928a3
Merge pull request #1916 from motec-research/spi_mmap
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SPIMMAP bug fixes and new features
2024-04-12 10:38:05 +02:00
a891b2dd11
Merge pull request #1904 from machdyne/master
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litex_json2dts_linux: Add support for multiple Ethernet interfaces
2024-04-12 10:32:12 +02:00
5d895bd3a7
Merge branch 'master' into master
2024-04-12 10:32:05 +02:00
441d05ee36
core/hyperbus: Start testing Register writes.
2024-04-11 18:39:48 +02:00
59756b4342
cores/hyperbus: Test and fix HyperRAM register read accesses.
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Seems OK:
Identification Register 0 : 00000e76
Identification Register 1 : 00000009
Configuration Register 0 : 00008f2f
Configuration Register 1 : 0000ffc1
reg_control: 302
reg_status: 2
reg_debug: 8
2024-04-11 18:29:48 +02:00
2384d6fbd4
cores/hyperbus: Add initial HyperRAM Register access over CSRs.
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Will be used to get HyperRAM characteristics and also to configure latency and enable varialble latency.
Untested yet.
2024-04-11 17:51:47 +02:00
b8ca87ece5
build/openocd: disabled 'poll off' because not supported by ECP5
2024-04-11 15:13:52 +02:00
62cf95c5da
cpu/vexii add git
2024-04-10 12:21:47 +02:00
555f89c22a
set default l2 ways to 4
2024-04-08 17:16:15 +02:00
9654b40864
Got litex dma to work with vexii
2024-04-08 16:45:15 +02:00
8f86108eed
tools/litex_json2dts add vexiiriscv
2024-04-08 14:40:44 +02:00
6885770e47
Uart tx irq handling fix
2024-04-07 17:39:30 +03:00
3864615f6f
tools/litex_json2dts_linux.py: improved cpu_isa_extension attribute (fdc) and fixed kernel panic during rocket booting with linux
2024-04-06 08:13:56 +02:00
06009c57a3
build/xilinx/common: Fix missing clk parameter on XilinxSDRTristateImpl.
2024-04-05 16:04:29 +02:00
5ae098ebc6
test/spi_mmap: be less verbose
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don't print miso/mosi changes with -v
2024-04-05 12:35:47 +11:00
c2da8de7b0
test_spi_mmap: tests for slot 0&1
2024-04-05 12:35:47 +11:00
07cfda119d
interconnect/wishbone: check err in simulation
2024-04-05 12:35:47 +11:00
416f1b4281
cores/spi_mmap: add slot post transfer cs_wait
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Also remove unused slot_status - maintains CSR alignment now that
slot_control is 64 bit (two 32bit registers).
2024-04-05 12:35:47 +11:00
f3b287addd
cores/spi_mmap: add 24-bit slot length
2024-04-05 12:31:39 +11:00
5d1fa7b6ca
cores/spi_mmap: fix data if bus width > length
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Details:
* 32bit bus write to 8 and 16bit MSB first slot resulted
in shifted data on mosi.
* 32bit read from 8 and 16bit LSB first slot resulted
with shifted data in fifo.
Fixes 2 tests - all current tests now pass.
2024-04-05 12:31:39 +11:00
422b02cc16
cores/spi_mmap: fix data in unused rx_fifo bits
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clear miso at start. Prevent previous transfer data in unused bits
with 8 and 16bit slot lengths and 32bit bus read. Fixes 2 tests.
2024-04-05 12:31:39 +11:00
a9c007d8d7
test/spi_mmap: add some SPIMMAP tests
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Some pass and some fail demonstrating issues observed in driver
development.
run unittest with -v to see more test details.
Ran 9 tests in 4.161s
FAILED (failures=4)
2024-04-05 12:31:39 +11:00
4bc47c959f
test/spi_mmap: lint and autoformat with Ruff
2024-04-05 12:31:39 +11:00
2e67f6a1a3
soc/cores/spi_mmap: add read only slot count register
2024-04-05 12:31:39 +11:00
3477aeaca1
soc/cores/spi_mmap: add read only version register
2024-04-05 12:31:39 +11:00
Florent Kermarrec
Gwenhael Goavec-Merou
Charles-Henri Mousset
Dolu1990
Dmitry Derevyanko
Andrew Dennison
Richard Tucker