9 commits

Author	SHA1	Message	Date
Florent Kermarrec	47b5ff5e33	move code and create a directory for each layer	2014-11-03 17:38:12 +01:00
Florent Kermarrec	25e0ccae9a	remove DRP ports (won't be used for now)	2014-10-28 11:33:15 +01:00
Florent Kermarrec	3f7406a937	various fixes and simplifications, SATA1 & SATA2 OK	2014-10-28 02:15:19 +01:00
Florent Kermarrec	f5001751d0	instanciate GTXE2_COMMON (seems recommended in AR43339)	2014-09-30 10:57:52 +02:00
Florent Kermarrec	d47917e480	simplify and clean up	2014-09-30 00:50:03 +02:00
Florent Kermarrec	2f769e4e4e	gtx: add resynchronization on control signals	2014-09-27 17:26:05 +02:00
Florent Kermarrec	f23c5aa724	mmcm: configure default divider with default_speed	2014-09-27 16:22:40 +02:00
Florent Kermarrec	45f7f8aff5	add tx_reset_fsm and rx_reset_fsm	2014-09-27 16:10:39 +02:00
Florent Kermarrec	c27f24c4c0	reorganize code ... - use sys_clk of 166.66MHz and using it instead of sata clk. - rename clocking to CRG since it also handles resets. - create datapath and move code from gtx.	2014-09-27 15:34:28 +02:00

Renamed from lib/sata/k7sataphy/clocking.py (Browse further)