Sebastien Bourdeauducq
|
d2c4afe66c
|
asmicon: various fixes. Now produces convincing refresh/read sequences.
|
2012-04-01 23:24:24 +02:00 |
|
Sebastien Bourdeauducq
|
f5671c566f
|
tb/asmicon: global test bench
|
2012-04-01 23:23:45 +02:00 |
|
Sebastien Bourdeauducq
|
185bd66ee4
|
tb/asmicon: bankmachine test bench
|
2012-03-31 18:11:29 +02:00 |
|
Sebastien Bourdeauducq
|
b1e5b9ef36
|
tb/asmicon/bankmachine: test buffer and NACK
|
2012-03-31 10:06:44 +02:00 |
|
Sebastien Bourdeauducq
|
c129c98e10
|
tb/asmicon/bankmachine: selector test bench
|
2012-03-31 09:56:22 +02:00 |
|
Sebastien Bourdeauducq
|
ac7d89a4fe
|
asmicon/bankmachine: fixes
|
2012-03-31 09:55:52 +02:00 |
|
Sebastien Bourdeauducq
|
bccc5f5c21
|
tb: remove obsolete norflash test bench
|
2012-03-30 16:41:12 +02:00 |
|
Sebastien Bourdeauducq
|
c6a4a8f462
|
tb/asmicon: refresher test
|
2012-03-30 16:40:51 +02:00 |
|
Sebastien Bourdeauducq
|
cd82f16806
|
asmicon/refresher: fix refresh sequence done signal
|
2012-03-30 16:26:50 +02:00 |
|
Sebastien Bourdeauducq
|
ab799b874f
|
tools: new flterm
|
2012-03-21 09:11:43 +01:00 |
|
Sebastien Bourdeauducq
|
c26efa28ca
|
asmicon: multiplexer (untested)
|
2012-03-18 22:11:01 +01:00 |
|
Sebastien Bourdeauducq
|
0e00837f42
|
asmicon: move slot time to timing settings
|
2012-03-18 14:57:31 +01:00 |
|
Sebastien Bourdeauducq
|
b1eb919ad2
|
asmicon: bank machine (untested)
|
2012-03-18 00:12:03 +01:00 |
|
Sebastien Bourdeauducq
|
7c377880fa
|
asmicon: refresher (untested)
|
2012-03-15 20:29:26 +01:00 |
|
Sebastien Bourdeauducq
|
e3ef121440
|
norflash: use new timeline API
|
2012-03-15 20:26:04 +01:00 |
|
Sebastien Bourdeauducq
|
7b14e0bd05
|
asmicon: skeleton
|
2012-03-14 18:26:05 +01:00 |
|
Sebastien Bourdeauducq
|
8d4a42887e
|
ddrphy: working on hardware, simulation a bit messed up
|
2012-02-24 15:44:51 +01:00 |
|
Sebastien Bourdeauducq
|
baba267db6
|
ddrphy: request wrdata_en/rddata_en at the same time as the command
|
2012-02-24 15:14:58 +01:00 |
|
Sebastien Bourdeauducq
|
17b2588321
|
ddrphy: reads OK, write data coming out 1/2 cycle too late
|
2012-02-24 15:05:52 +01:00 |
|
Sebastien Bourdeauducq
|
a363eb4a36
|
ddrphy: partly working
|
2012-02-24 13:54:10 +01:00 |
|
Sebastien Bourdeauducq
|
3179a27d14
|
dfii: set data mask
|
2012-02-23 22:00:51 +01:00 |
|
Sebastien Bourdeauducq
|
92ac69bae3
|
dfii: new design
|
2012-02-23 21:21:07 +01:00 |
|
Sebastien Bourdeauducq
|
b3ca952a39
|
s6ddrphy: read path OK in simulation
|
2012-02-21 17:38:40 +01:00 |
|
Sebastien Bourdeauducq
|
b4e041ecf1
|
s6ddrphy: write path OK in simulation
|
2012-02-20 23:55:20 +01:00 |
|
Sebastien Bourdeauducq
|
ce51653381
|
s6ddrphy: generate DQ/DQS/DM OE
|
2012-02-20 16:13:56 +01:00 |
|
Sebastien Bourdeauducq
|
cbc3b7fa83
|
s6ddrphy: DQ/DQS/DM SERDES
|
2012-02-20 13:45:57 +01:00 |
|
Sebastien Bourdeauducq
|
4c1e18a9b5
|
s6ddrphy: clock, address and command
|
2012-02-19 20:49:56 +01:00 |
|
Sebastien Bourdeauducq
|
f35cd4a85b
|
Prepare for new DDR PHY
|
2012-02-19 18:43:42 +01:00 |
|
Sebastien Bourdeauducq
|
1e4e092a55
|
bios: fix function prototypes
|
2012-02-18 21:06:35 +01:00 |
|
Sebastien Bourdeauducq
|
026457a98c
|
Send SDRAM initialization sequence and answer PHY read/write requests. Obstinately refuses to work, unfortunately.
|
2012-02-18 18:12:14 +01:00 |
|
Sebastien Bourdeauducq
|
5bc840b9c1
|
DFI injector (untested)
|
2012-02-17 23:50:10 +01:00 |
|
Sebastien Bourdeauducq
|
c38de34a21
|
bios: DDR initialization skeleton
|
2012-02-17 18:47:04 +01:00 |
|
Sebastien Bourdeauducq
|
e5927e265f
|
bios: add flash target using m1nor
|
2012-02-17 18:16:29 +01:00 |
|
Sebastien Bourdeauducq
|
48ddbf0c85
|
Add build Makefile and JTAG load script
|
2012-02-17 18:09:48 +01:00 |
|
Sebastien Bourdeauducq
|
c387ce7ce5
|
Map DDR PHY controls in CSR
|
2012-02-17 17:34:59 +01:00 |
|
Sebastien Bourdeauducq
|
5d1dad583b
|
Connect DDR PHY
Doesn't do much for the moment, just to check synthesis/P&R.
|
2012-02-17 11:04:44 +01:00 |
|
Sebastien Bourdeauducq
|
cdd58e023b
|
s6ddrphy: use single-ended DQS
|
2012-02-17 10:53:58 +01:00 |
|
Sebastien Bourdeauducq
|
cc5e4ae710
|
clkfx: remove
|
2012-02-16 19:30:00 +01:00 |
|
Sebastien Bourdeauducq
|
204452b0d3
|
m1crg: make clock feedback pin bidirectional
|
2012-02-16 18:35:44 +01:00 |
|
Sebastien Bourdeauducq
|
f36a45edcb
|
lm32: compatibility with the new instance API
|
2012-02-16 18:35:22 +01:00 |
|
Sebastien Bourdeauducq
|
72f9af9d90
|
Generate all clocks for the DDR PHY
|
2012-02-16 18:02:37 +01:00 |
|
Sebastien Bourdeauducq
|
859c9d8849
|
Use new bus API
|
2012-02-15 16:55:13 +01:00 |
|
Sebastien Bourdeauducq
|
1368b666df
|
s6ddrphy: prepare quilt
|
2012-02-14 15:52:39 +01:00 |
|
Sebastien Bourdeauducq
|
b157d84434
|
README
|
2012-02-14 15:43:09 +01:00 |
|
Sebastien Bourdeauducq
|
aef2e4b5e8
|
Use double quotes for all strings
|
2012-02-14 13:15:00 +01:00 |
|
Sebastien Bourdeauducq
|
5165ff7ec3
|
Include Wishbone to ASMI bridge
|
2012-02-13 23:12:57 +01:00 |
|
Sebastien Bourdeauducq
|
0654bf4583
|
tools: use install and /usr/local (as suggested by David Kuehling)
|
2012-02-08 15:09:07 +01:00 |
|
Sebastien Bourdeauducq
|
bfd2bf4ed3
|
tools: remove bin2hex
|
2012-02-08 15:08:03 +01:00 |
|
Sebastien Bourdeauducq
|
755079d7fa
|
libbase: blocking UART write if IRQs are enabled
|
2012-02-07 15:12:27 +01:00 |
|
Sebastien Bourdeauducq
|
73fce59631
|
software: shell from original BIOS
|
2012-02-07 15:02:44 +01:00 |