It's only boot tested in sim and build tested in Vivado now, and it
requires a FPGA > 100k LUT4 (XC7A100T currently does not fit).
The ISR code is based on Rocket one.
These Python code depends on a forked version of OpenC906 at [1].
[1] https://github.com/Icenowy/openc906/tree/fpga-optimization
Signed-off-by: Icenowy Zheng <uwu@icenowy.me>
Quartus software wants a derive_pll_clock sentence in SDC file to enable
automatic PLL clock derivation, and by test this sentence is harmless
even when no PLL exists.
Add this sentence to to the generated SDC file.
Signed-off-by: Icenowy Zheng <uwu@icenowy.me>
The N factor is currently ignored when creating ALTPLL instance.
As Quartus will internally decide N based on all dividers, just multiply
N to all clock outputs' individual divider.
Signed-off-by: Icenowy Zheng <uwu@icenowy.me>
Reuse of external defined CSR_BASE has been added for some use-cases, allowing more
flexilibity but also complicating direct read of base addresses for users in csr.h.
with_csr_base_define parameter has been added, allowing disabling CSR_BASE #define/reuse
when set to False.
Instead of enabling the zicsr extension in crt0.S, change -march to
specify that VexRISCV implements version 2.0 of I, rather than the
latest (2.1). In 2.0 the csr instructions were still part of I.
This approach has two advantages:
* It is compatible with older versions of binutils, since they do not
need to know about the new zicsr extension
* By modifying the -march in CFLAGS, csr instructions can be used in any
code (for example by the inline functions in irq.h), not just in crt0.S.
Also use --opt-level=O0 to reduce compilation time (execution is a bit slower but since we are only
executing the BIOS here, total test time is still reduced).
uint32_t is treated as `unsigned int` by the 64-bit compiler, and
as `long unsigned int` by the 32-bit compiler. As such, we'll get
a warning on one or the other regardless of whether we use "%ld"
or "%d" with printf:
on 64-bit (rocket, using "%ld"):
./litex/litex/soc/software/liblitesata/sata.c: In function 'sata_init':
./litex/litex/soc/software/liblitesata/sata.c:87:45:
warning: format '%ld' expects argument of type 'long int', but
argument 2 has type 'uint32_t' {aka 'unsigned int'} [-Wformat=]
87 | printf("Capacity: %ldGB\n", capacity);
| ~~^ ~~~~~~~~
| | |
| | uint32_t {aka unsigned int}
| long int
| %d
on 32-bit (vexriscv, using "%d"):
./litex/litex/soc/software/liblitesata/sata.c: In function 'sata_init':
./litex/litex/soc/software/liblitesata/sata.c:87:44:
warning: format '%d' expects argument of type 'int', but
argument 2 has type 'uint32_t' {aka 'long unsigned int'} [-Wformat=]
87 | printf("Capacity: %dGB\n", capacity);
| ~^ ~~~~~~~~
| | |
| int uint32_t {aka long unsigned int}
| %ld
This patch changes `capacity` to `unsigned`, which has the same size
as `uint32_t`, but has the advantage of being treated the same by
`printf` regardless of whether we use the 32- or 64-bit compiler.
Changes in Zephyr require updated script to generate correct overlay.
This commit splits CSR regions that were being added to overlay as
single register into separate registers with names.
It also prints their size in bytes instead of used subregisters.
I also added LITEX_CSR_DATA_WIDTH to generated config parameters.
To limit code duplication, I added functions used for indenting text.
Additionally, I updated formatting functions to take list of registers
and then format it, instead of just surrounding already formatted text
with braces.
- Cosmetic changes and increase similarities with other CPUs.
- Simplification.
- Allow converting AXI to Wishbone or AXI-Lite (Still keep wishbone as default).
- Connect reset from SoC.
- Reorder AXI signals by channels.
- Move JTAG integration to add_jtag method.
Icenowy Zheng
Florent Kermarrec
Mikołaj Sowiński
Andrew E Wilson
Jevin Sweval
Dolu1990
Marcus Comstedt
Gabriel Somlo
Tim 'mithro' Ansell
Michal Sieron