Robert Jordens
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5953f901c8
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spiflash: add read-only variable data width spi flash
Signed-off-by: Robert Jordens <jordens@gmail.com>
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2013-11-25 14:23:55 +01:00 |
Sebastien Bourdeauducq
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96600ad9d7
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set LM32 reset address
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2013-11-25 12:09:16 +01:00 |
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Sebastien Bourdeauducq
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7459a849ee
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IntegratedBIOS: read only
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2013-11-25 10:25:05 +01:00 |
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Sebastien Bourdeauducq
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78cd7a288e
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move integrated BIOS code to gensoc
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2013-11-25 10:22:14 +01:00 |
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Sebastien Bourdeauducq
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b212e0279d
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gensoc: add Papilio Pro ID
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2013-11-24 23:50:33 +01:00 |
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Sebastien Bourdeauducq
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257185cc9c
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rename create_sdram_modules and add register_rom
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2013-11-24 20:16:19 +01:00 |
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Sebastien Bourdeauducq
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fca0b968e7
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generate linker memory map, move all generated files into the same folder
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2013-11-24 19:50:17 +01:00 |
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Sebastien Bourdeauducq
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fdff1ae5f8
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make build system more generic
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2013-11-24 13:37:32 +01:00 |
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Sebastien Bourdeauducq
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4a3a1d02e9
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modularize SoC integration
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2013-11-24 10:30:02 +01:00 |
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Sebastien Bourdeauducq
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7496ba6360
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framebuffer: fix resynchronization after resolution change
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2013-11-21 00:33:22 +01:00 |
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Sebastien Bourdeauducq
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96fcb3574e
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Revert "framebuffer: reset VTG"
This reverts commit 6cb18f5ce3.
Conflicts:
misoclib/framebuffer/__init__.py
misoclib/framebuffer/format.py
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2013-11-19 23:48:00 +01:00 |
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Sebastien Bourdeauducq
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2eabf97147
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dvisampler: transfer the last word in frames correctly
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2013-11-19 23:38:48 +01:00 |
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Sebastien Bourdeauducq
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de76e91147
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framebuffer: expose PLL DRP to CSR
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2013-11-18 20:32:33 +01:00 |
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Sebastien Bourdeauducq
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9e883b8b02
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dvisampler: expose PLL DRP to CSR
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2013-11-18 20:32:21 +01:00 |
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Sebastien Bourdeauducq
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4cfcda6c8c
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framebuffer: unpack memory words in pixel clock domain for better perf
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2013-11-17 23:41:18 +01:00 |
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Sebastien Bourdeauducq
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c3d0985fb2
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add L2 cache size in identifier + function to flush L2
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2013-11-16 16:27:21 +01:00 |
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Sebastien Bourdeauducq
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6f990a017e
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dvisampler: pack pixels in pixel clock domain to improve performance
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2013-11-16 13:53:26 +01:00 |
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Sebastien Bourdeauducq
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6cb18f5ce3
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framebuffer: reset VTG
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2013-11-15 11:25:07 +01:00 |
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Sebastien Bourdeauducq
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34e8e8c259
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dvisampler: update address CSR at end of DMA
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2013-11-13 18:57:10 +01:00 |
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Sebastien Bourdeauducq
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15499560b5
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cpuif: add memories to csr.h
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2013-11-11 16:53:00 +01:00 |
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Sebastien Bourdeauducq
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75d25af3aa
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cosmetic changes
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2013-11-10 16:12:24 +01:00 |
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Robert Jordens
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31ec33dbad
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s6ddrphy: use shorter Instance argument notation
Signed-off-by: Robert Jordens <jordens@gmail.com>
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2013-11-10 12:52:03 +01:00 |
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Robert Jordens
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c1e5683ba2
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s6ddrphy: drop unused outputs, shortens verilog and produces more readable warnings
Signed-off-by: Robert Jordens <jordens@gmail.com>
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2013-11-10 11:13:36 +01:00 |
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Robert Jordens
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05944cf909
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cpuif.py: add _ADDR and _SIZE defines for each register
Signed-off-by: Robert Jordens <jordens@gmail.com>
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2013-11-10 10:44:39 +01:00 |
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Sebastien Bourdeauducq
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d7a4d8b66e
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use git commit id as version
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2013-11-09 16:38:44 +01:00 |
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Sebastien Bourdeauducq
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0b881d934f
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rename milkymist-ng to MiSoC
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2013-11-09 15:27:32 +01:00 |