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9392 Commits

Author SHA1 Message Date
Florent Kermarrec d165418719 CHANGES.md: Update. 2023-09-12 09:35:53 +02:00
Florent Kermarrec bcc7e56dc6 build/efinix/common: Add EfinixClkInput/Ouptut to use then in RGMII PHYs and avoid duplicating block code. 2023-09-12 09:30:45 +02:00
Florent Kermarrec 412f0f59b9 build/io: Add ClkInput/Ouptut to be able to abstract Clk Input/Output primitives. 2023-09-12 09:29:45 +02:00
Florent Kermarrec 36ce71d59b clock/efinix: Avoid manual n parameter and handle it internally. 2023-09-11 10:11:58 +02:00
Dolu1990 112f78bde3 cores/vexriscv_smp add risc-v official debug support via --with-privileged-debug 
Using https://github.com/SpinalHDL/NaxRiscv/blob/main/src/main/tcl/openocd/naxriscv_jtag_tunneled.tcl
 2023-09-08 16:42:09 +02:00
Florent Kermarrec 022bdf3cdc tools/litex_client: Add binary mode to read_memory and fix hex/binary prefix in dump_registers. 2023-09-08 16:12:04 +02:00
Florent Kermarrec 6c30cb8695 litex_setup.py: Use fixed sha1 version of Migen. 
Migen switched from setup.py to pyproject.toml, we'll need to handle this.
 2023-09-08 10:41:30 +02:00
Florent Kermarrec fbae6e8e37 CHANGES.md: Update. 2023-09-07 14:27:12 +02:00
enjoy-digital e1025c610a
Merge pull request #1769 from Icenowy/gw5a-pll-fix 
clock/gowin_gw5a: change allowed frequency range for GW5A- prefix
 2023-09-06 09:15:42 +02:00
enjoy-digital e185871267
Merge pull request #1767 from josuah/fix_radiant_platform_detection 
build/lattice/radiant: fix uname() not prefixed by 'os.'
 2023-09-06 09:15:01 +02:00
Dolu1990 72447a1f49 Merge remote-tracking branch 'origin/master' into nax-smp 
# Conflicts:
#	litex/soc/cores/cpu/naxriscv/core.py
#	litex/soc/integration/soc.py
 2023-09-05 18:14:44 +02:00
Dolu1990 943d652362 cores/naxriscv match axi width 2023-09-05 18:13:27 +02:00
Gwenhael Goavec-Merou 99cb46fd3e build/efinix/ifacewriter: fix CLKOUTx_PHASE configuration for recent efinity, keep backward compatibility 2023-09-05 16:44:47 +02:00
Icenowy Zheng 7afe06a60c clock/gowin_gw5a: change allowed frequency range for GW5A- prefix 
When targeting GW5A-25 ES, the Gowin IDE has a more strict frequency
range.

Change the range when GW5A- is matched to this.

Signed-off-by: Icenowy Zheng <uwu@icenowy.me>
 2023-09-05 16:50:49 +08:00
Josuah Demangeon 5e4628f1fe build/lattice/radiant: fix uname() not prefixed by 'os.' 2023-09-04 19:30:29 +02:00
enjoy-digital 6c6cfeae7f
Merge pull request #1763 from josuah/radiant_wsl2 
Allow use of Windows-side (.exe) Radiant toolchain
 2023-09-03 19:27:32 +02:00
Josuah Demangeon 2e6ddd9dd9 build/lattice/radiant: allow use of Windows-side (.exe) radiant toolchain under WSL2 2023-09-02 22:28:40 +02:00
Dolu1990 8853215033
Merge pull request #1762 from motec-research/dma_fix 
proof of concept coherent dma fix
 2023-09-02 08:22:40 +02:00
Andrew Dennison 1bb4d299a6 vexrisc_smp: fix DMA bus address_width calculation 2023-09-02 11:46:11 +10:00
Andrew Dennison 48ab96fd43 soc/intregation: fix cpu name in logging 
Fixed CPU name being reported as irq name in logging.

```
INFO:SoC:CPU vexriscv_smp adding Interrupt(s).
INFO:SoCIRQHandler:noirq IRQ added at Location 0.
INFO:SoC:CPU noirq adding DMA Bus.
INFO:SoCDMABusHandler:Creating Bus Handler...
```
 2023-09-02 11:46:11 +10:00
Florent Kermarrec 57faa9102f CHANGES: Update. 2023-09-01 12:40:03 +02:00
Florent Kermarrec f473261bc6 soc/dma_bus: Make SoCDMABusHandler use the Bus Standard of the DMA Bus defined in the CPU. 
Also simplify code by using automatic Bus conversion of SoCBusHandler.
 2023-09-01 12:19:11 +02:00
Florent Kermarrec db2ad78860 interconnect/wishbone: Add address_width property to make sure all interfaces (Wishbone/AXI-Lite/AXI) have it. 2023-09-01 12:16:15 +02:00
enjoy-digital 33efa09663
Merge pull request #1760 from motec-research/dts_linux_fix 
tools/litex_json2dts_linux: fix missed sdcard_ references
 2023-09-01 10:46:04 +02:00
Richard Tucker 058cdd646b tools/litex_json2dts_linux: fix missed sdcard_ references 2023-09-01 16:54:41 +10:00
enjoy-digital 14012263af
Merge pull request #1758 from motec-research/spi_mmap_fix 
soc/cores/spi_mmap: Fix clock divider
 2023-09-01 08:38:53 +02:00
Radek Pesina d494e30166 soc/cores/spi_mmap: Fix clock divider 2023-09-01 12:34:51 +10:00
Florent Kermarrec 405296b7fd interconnect/axi/axi_full: Fix missing switch to LiteXModule. 2023-08-31 19:36:21 +02:00
Gwenhael Goavec-Merou 516038ce76 soc/cores/clock/efinix: don't hardcore create_clock (fix warning because clock is created after set_false_path), explicit clock name (fix warning when signal is absorbed) 2023-08-31 17:24:58 +02:00
Gwenhael Goavec-Merou fadf47d353 build/lattice/trellis: fix add_period_constraint signature (missing keep arg) 2023-08-31 16:52:48 +02:00
Florent Kermarrec 41357aba7d xilinx/vivado: Fix issue with #1755. 2023-08-31 16:38:50 +02:00
Florent Kermarrec ad924a522a interconnect/stream/AsyncFIFO: Remove Efinix workaround since seems to be solved with Efinity 2023.x. 2023-08-31 16:03:52 +02:00
enjoy-digital 124e0d22c9
Merge pull request #1755 from enjoy-digital/allows_clk_name_override 
build/xx/toolchains: allows override clock naming
 2023-08-31 15:57:39 +02:00
Gwenhael Goavec-Merou 46800176ae build/xx/toolchains: allows override clock naming 2023-08-31 15:18:15 +02:00
Gwenhael Goavec-Merou 2a7caa2696 build: all platforms: override add_period_constraint only when required 2023-08-31 12:29:09 +02:00
Gwenhael Goavec-Merou 3f43481eb9 build/efinix/efinity: build_timing_constraints: set_false_path is unidirectional -> add another one to -> from_ 2023-08-31 11:42:07 +02:00
Gwenhael Goavec-Merou a071cc343d litex/soc/integration/soc: add_etherxx: when eth_rx_clk is eth_tx_clk only apply constraints on eth_rx_clk 2023-08-31 11:36:24 +02:00
Florent Kermarrec 9854c9f322 CHANGES: Update. 2023-08-30 18:11:11 +02:00
Florent Kermarrec ff0df100e9 build/efinix: Add get_pin (from sig) to EfinixPlatform and use it to simplify/fix IOs exclusion. 2023-08-30 18:08:40 +02:00
Florent Kermarrec 72590dfde3 software/libliteeth: Fix udp_set_callback warning. 2023-08-30 17:44:00 +02:00
Florent Kermarrec 434e2225ea software/liblitedram: Fix swap_bit warning. 2023-08-30 17:22:57 +02:00
Florent Kermarrec c2714df198 build/efinix/common: Add initial EfinixDDROutput/EfinixDDRInput implementation. 
Still need to figure out a few things:
- Clk is passed as a string for now.
- IOs exclusion still handled externally.
 2023-08-30 11:28:48 +02:00
Florent Kermarrec c0ab4ed1c1 build/io: Allow passing clk as str on DDRInput/Output, wrap DDROutput IOs and minor ident fixes. 2023-08-30 10:52:13 +02:00
Florent Kermarrec 6dff371835 build/efinix/common: Simplify IO exclusion in EfinixTristateImpl and fix corner cases (ex eth_mdio that was not automatically excluded). 2023-08-30 09:16:46 +02:00
Florent Kermarrec 9528f89d45 CHANGES: Update. 2023-08-29 17:15:45 +02:00
Florent Kermarrec 85dadb827a clock/gowin_gw5a: Fix copyright. 2023-08-29 14:25:04 +02:00
enjoy-digital c122fef5ac
Merge pull request #1741 from Icenowy/gw5apll 
soc/cores/clock: initial GW5A support
 2023-08-29 14:21:02 +02:00
Icenowy Zheng 1636c0ef8d soc/cores/clock: initial GW5A support 
GW5A has different PLLs than GW1N/GW2A, with multiple individual
ODIV's. GW5A-25 has a different PLL with GW5A[S]T-138, with lack of
dynamic control.

Add basic support for them.

Signed-off-by: Icenowy Zheng <uwu@icenowy.me>
 2023-08-29 15:39:25 +08:00
Dolu1990 a4498dcd03 nax dma wip, WARNING soc.py 2023-08-28 18:57:45 +02:00
Florent Kermarrec 82602f660c interconnect/stream: Fix #1736. 2023-08-28 16:19:31 +02:00