Commit Graph

8545 Commits

Author SHA1 Message Date
Arne Jansen 647504d4c5 align fixup 2023-01-30 07:46:37 +01:00
Arne Jansen 72ec359f52 soc: allow regions that are not a power of 2
Align region to its power of 2, not the region size itself.
2022-12-20 10:32:56 +01:00
enjoy-digital d504639f1c
Merge pull request #1538 from jevinskie/jev/bug/mac-arm64-sim-module-build-fix
Fix sim module build on MacOS arm64
2022-12-16 10:58:06 +01:00
Jevin Sweval e393f84799 Fix sim module build on MacOS arm64 2022-12-15 11:27:32 -05:00
enjoy-digital f007f812df
Merge pull request #1537 from trabucayre/fix_windows_build
build/nextpnr_wrapper,yosys_nextpnr_toolchain,yosys_wrapper: fix LF for windows (#1536)
2022-12-15 09:40:26 +01:00
Gwenhael Goavec-Merou d17041e076 build/nextpnr_wrapper,yosys_nextpnr_toolchain,yosys_wrapper: fix LF for windows (#1536) 2022-12-14 22:04:40 +01:00
Florent Kermarrec cb85a8caf1 tools/litex_cli: Fix --write. 2022-12-12 11:26:37 +01:00
enjoy-digital 30d68ce152
Merge pull request #1535 from Icenowy/c906-extcsr
cpu/openc906: set extended CSRs based on D1 configuration
2022-12-12 11:23:47 +01:00
Icenowy Zheng 83aa3c031b cpu/openc906: set extended CSRs based on D1 configuration
Copy all feature and performance related CSR configuration from
sun20i_d1_spl, which are values Allwinner suggests for D1 SoC.

Signed-off-by: Icenowy Zheng <uwu@icenowy.me>
2022-12-09 20:21:27 +08:00
Florent Kermarrec 78fbb64c18 cpu/cva6/core: Remove convert_periph_bus_to_wishbone since no longer required. 2022-12-09 13:16:50 +01:00
Florent Kermarrec 879207f4d7 interconnect/axi/axi_full/AXIDownConverter: Add convert_addr/burst/len/size helpers and fix size conversion. 2022-12-09 13:09:52 +01:00
Richard Tucker 2bab1a6b03 efinix:ifacewriter: fix JTAG generation 2022-12-09 10:59:48 +01:00
Florent Kermarrec 497eac09a0 test/test_axi/test_axi_width_converter: Rename and cleanup. 2022-12-08 21:39:08 +01:00
Florent Kermarrec 0f95d04052 test/test_axi/test_axi_width_converter: Switch to DUT. 2022-12-08 18:54:59 +01:00
Florent Kermarrec fd12b6b0b7 interconnect/axi/axi_full/AXIDownConverter: Fix len/addr conversion and add latency to r.resp/user/dest/id. 2022-12-08 18:52:29 +01:00
Florent Kermarrec a54d5180ba test/test_axi/test_axi_width_converter: Use address_width on Wishbone.Interface to simplify. 2022-12-08 16:23:15 +01:00
Florent Kermarrec fac9fb81a2 gen/fhdl/module: Add add/get_module methods to simplify user design and avoid direct use of setattr/getattr. 2022-12-08 14:20:38 +01:00
enjoy-digital 9bf276132a
Merge pull request #1499 from Icenowy/liblitedram-refine
Some small changes to liblitedram
2022-12-08 10:33:58 +01:00
enjoy-digital d6bbf655ee
Merge pull request #1527 from stone3311/master
software/demo: Add .got and .toc to .rodata in linker script
2022-12-06 11:54:03 +01:00
enjoy-digital 8599e2704d
Merge pull request #1529 from trabucayre/parser_set_defaults
build/parser: overrides set_defaults and applying default values just before args_parse()
2022-12-06 11:53:08 +01:00
Gwenhael Goavec-Merou 7eed962661 build/parser: overrides set_defaults and applying default values just before args_parse() 2022-12-05 20:37:12 +01:00
Gabriel Somlo 937428b1fc cpu/rocket: add "octo" (512 bit wide) "full" variants
Boards such as the Xilinx VC707, STLV7325, etc. offer support for
dual-rank memory, which results in a 512-bit wide native LiteDRAM
port. These additional "8x wide" (or "octo") variants support that
width directly, without the need for additional data width conversion
that whould have to be implemented on the LiteX side of the SoC.

Suggested-by: Icenowy Zheng <uwu@icenowy.me>
Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
2022-12-04 07:58:03 -05:00
stone3311 213a16c77e software/demo: Add .got and .toc to .rodata in linker script 2022-12-04 13:19:52 +01:00
enjoy-digital 85f762cd1c
Merge pull request #1526 from gsomlo/gls-mem-axi-width-warn
integration/soc: Warn on MemBus <-> LiteDRAM AXI width conversion
2022-12-03 21:58:54 +01:00
Gabriel Somlo be40e796f2 integration/soc: Warn on MemBus <-> LiteDRAM AXI width conversion
CPUs with a dedicated memory port (MemBus) are typically connected
directly to the LiteDRAM port. Some models (e.g., Rocket) come in
(otherwise equivalent) variants specifically pre-generated to fit
the various "standard" LiteDRAM port widths (so far, 64, 128, or
256 bits).

This patch introduces a warning when the CPU variant's dedicated
MemBus doesn't exactly match the width of LiteDRAM, requiring
explicit conversion.

The goal is to inform the user and provide them with an opportunity
to pick a more suitable CPU variant (of matching MemBus width), if
available.
2022-12-02 10:41:40 -05:00
Dolu1990 fe7e70baa9
Merge pull request #1521 from enjoy-digital/naxriscv-merge
cpu/NaxRiscv : Update with a smaller LSU, lower latency FPU, self-healing RAS
2022-12-01 16:10:46 +01:00
Dolu1990 17570f85c0 cpu/NaxRiscv : fix atomic / interrupt deadlock 2022-12-01 11:04:45 +01:00
Florent Kermarrec 7a0056ebf6 cores/ecc: Add initial doc with the help of our new assistant and to test its capabilities :) 2022-12-01 10:27:05 +01:00
Florent Kermarrec c0f31dc843 integration/soc_core: Add default value to soc_core_argdict/ident_version. 2022-11-30 08:46:42 +01:00
Dolu1990 d32149d1a6 Merge branch 'master' into naxriscv-merge 2022-11-25 18:27:12 +01:00
Dolu1990 bf279c0092 cpu/NaxRiscv fix LSU sqcheck 2022-11-25 18:06:13 +01:00
Dolu1990 d5b500762b cpu/NaxRiscv : Update with a smaller LSU, lower latency FPU, self-healing RAS 2022-11-25 16:30:53 +01:00
Gwenhael Goavec-Merou 310bc777b4
Merge pull request #1520 from mkuhn99/master
Zynq7000: Implement function to add axi gp slave
2022-11-23 19:30:38 +01:00
mkuhn99 2630ccbc43 impemented add_axi_gp_slave function for zynq7000 core 2022-11-23 17:02:42 +01:00
Florent Kermarrec 143e08575c build/xilinx/vivado: Cleanup location of bistream/additional commands. 2022-11-23 11:17:00 +01:00
Florent Kermarrec f9d2eec06f integration/export: Directly generate extract/replace mask in Python (Fix compilation warning with size=32). 2022-11-22 10:13:22 +01:00
Florent Kermarrec c8197b1842 integration/export: Fix CSR base address definition when with_csr_base_define=False.
We don't want base address to be function express with CSR_BASE but still want base address to be defined.
2022-11-21 17:57:48 +01:00
Florent Kermarrec 4b22a7b109 build/osfpga: Add fake OSFPGAAsyncResetSynchronizer and false_path_constraint to be able to generate more cores.
Code will be replaced when information will be available.
2022-11-21 12:31:06 +01:00
Florent Kermarrec 9a8c19d3b0 build/sim/verilator: Also exclude .init files. 2022-11-21 11:26:21 +01:00
Florent Kermarrec 2c9ddc20be ci: Switch GCC toolchain install to litex_setup.py (to also cover litex_setup.py GCC toolchain install in CI). 2022-11-21 09:20:22 +01:00
Florent Kermarrec dd91c55c36 litex_setup.py: Switch GCC toolchain install to distro install (When available). 2022-11-21 09:17:13 +01:00
enjoy-digital c4cf5d6fcd
Merge pull request #1519 from shenki/use-distro-compilers
github: Use distibution compilers for riscv and or1k
2022-11-21 09:16:02 +01:00
enjoy-digital 3d53f88262
Merge pull request #1518 from shenki/bump-microwatt
litex_setup: Update Microwatt to latest
2022-11-21 08:24:48 +01:00
enjoy-digital 9bb1a261dc
Merge pull request #1517 from shenki/nerov32
test_cpu: Add NeoRV32 to tested CPUs
2022-11-21 08:24:25 +01:00
Joel Stanley b30dd0b5c6 test_cpu: Add NeoRV32 to tested CPUs
With CI supporting GHDL to convert VHDL to Verilog the neorv32
simulation can be tested.

Fixes https://github.com/enjoy-digital/litex/issues/1320

Signed-off-by: Joel Stanley <joel@jms.id.au>
2022-11-21 15:20:49 +10:30
Joel Stanley 76f7cf8b52 github: Use distibution compilers for riscv and or1k
Signed-off-by: Joel Stanley <joel@jms.id.au>
2022-11-21 14:47:53 +10:30
Joel Stanley 8b7c569fac litex_setup: Update Microwatt to latest
Signed-off-by: Joel Stanley <joel@jms.id.au>
2022-11-21 14:41:01 +10:30
Florent Kermarrec 6b4696e3e0 soc/add_spi_flash: Use name as prefix for defined constants.
Allow adding multiple SPIFlash with different names to the SoC. The BIOS will
only use "spiflash" for now but the other SPI Flash core will  be accessible.
2022-11-18 18:31:19 +01:00
Florent Kermarrec c957ed6ed3 README.md: Update Discord invitation link (permanent). 2022-11-18 09:00:05 +01:00
enjoy-digital cc4ae21795
Merge pull request #1515 from shenki/ci-ubuntu-22.04
Update CI to use Ubuntu 22.04
2022-11-18 08:57:44 +01:00