34ed315a48
remove trailing whitespaces
2014-10-17 17:14:40 +08:00
d860813dec
use new direct access on endpoints
2014-10-16 17:57:30 +02:00
bbfce2b707
ctrl: drive txcomwake and not gtx.txcomwake in K7SATAPHYDeviceCtrl
2014-10-16 10:38:26 +02:00
9649b1497c
uart2wishbone: fix missing payload.d
2014-10-16 09:37:43 +02:00
2319ee0ab7
uart2wishbone: always use payload.d and not .d
2014-10-15 12:13:22 +02:00
027ddc65ca
fill __init__.py to simplify imports
2014-10-10 17:24:36 +02:00
bf95ea6c1c
mila: simplify usage
2014-10-10 16:17:12 +02:00
d0c9838dca
uart2wishbone: share UARTRX and UARTTX with MiSoC
2014-10-10 15:15:58 +02:00
20528c622a
mor1kx: sync
2014-10-10 15:38:05 +08:00
e53fb88b85
uart: minor cleanup and fix
2014-10-10 15:33:27 +08:00
5e5f436aa6
uart: split it and use dataflow
...
This make the code easier to understand and allow the reuse of UARTRX & UARTTX
on designs without CPU (e.g miscope).
2014-10-10 15:24:47 +08:00
ba30a01830
mila: fixes when used without RLE
2014-10-06 12:30:06 +02:00
f72f11f7b4
mila: add clk_domain support
...
an AsyncFIFO is inserted when clk_domain is not "sys" to enable capture from another clock domain.
sys_clk frequency need to be greater than clk_domain clock.
future possible improvement: automatic insertion of a converter when clk_domain frequency is
greater than sys_clk.
2014-10-06 12:07:20 +02:00
7043e6a5f3
mila: simplify export
2014-10-01 10:06:59 +02:00
b284819d18
revert simulation design and add wave
2014-09-30 11:10:15 +02:00
110580eb2e
add .payload. to Sink and Source to be compatible with upstream Migen
2014-09-30 11:03:36 +02:00
f5001751d0
instanciate GTXE2_COMMON (seems recommended in AR43339)
2014-09-30 10:57:52 +02:00
cf084fd079
test to visualize OOB with Miscope
2014-09-30 10:17:15 +02:00
bc5b23b808
use SGMII clk (125MHz) and SFP for test on KC705
2014-09-30 09:07:15 +02:00
d47917e480
simplify and clean up
2014-09-30 00:50:03 +02:00
0791b9e2e4
sim working
2014-09-29 17:12:02 +02:00
b47153fbfa
fix alignment (still some transmissions errors --> need to check clocks and resets)
2014-09-29 15:37:35 +02:00
ed752758b0
fix and simplify ctrl fsms, OOB OK, align KO
2014-09-27 17:45:46 +02:00
2f769e4e4e
gtx: add resynchronization on control signals
2014-09-27 17:26:05 +02:00
f23c5aa724
mmcm: configure default divider with default_speed
2014-09-27 16:22:40 +02:00
45f7f8aff5
add tx_reset_fsm and rx_reset_fsm
2014-09-27 16:10:39 +02:00
c27f24c4c0
reorganize code
...
- use sys_clk of 166.66MHz and using it instead of sata clk.
- rename clocking to CRG since it also handles resets.
- create datapath and move code from gtx.
2014-09-27 15:34:28 +02:00
879478a6e4
clocking: clean up and add comments
2014-09-27 13:33:43 +02:00
387cf90cf8
host and device communicate with OOB, now need to fix ctrl
2014-09-26 23:30:30 +02:00
01da43ecb2
reset and lock of PLL OK. We see OOB signals on the link but they are not decoded by the device.
2014-09-26 22:31:32 +02:00
dfbec91a62
add modelsim simulation and start fixing init
2014-09-26 17:05:05 +02:00
c1fc0b9c97
update README with new Kintex-7 support
2014-09-26 10:36:29 +08:00
13fb9282db
targets: add simple design (vendor agnostic and usable on all platforms with UART pins).
...
Designing a SoC with Migen is easy, but we have to provide a very simple design that can
be used on all boards with only 1 clock and 2 UARTs pins defined. This will encourage the
newcomer to invest time in Migen/MiSoC and see its real potential.
2014-09-26 10:35:15 +08:00
1d053bd7ee
modify TestDesign to be able to simulate phy with host <--> device loopback
2014-09-25 15:37:49 +02:00
7e14c4fc51
move some logic outside of GTX
2014-09-25 15:23:56 +02:00
c008dfdd98
clean up (thanks to Sebastien)
2014-09-25 14:17:25 +02:00
111f527647
do some clean up
2014-09-24 22:26:33 +02:00
2fb418a373
use new MiSoC UART with phase accumulators
...
this will allow to speed up MiLa reads
2014-09-24 21:56:15 +02:00
435bc22fa0
integrate phy in test design and start fix syntax errors
2014-09-24 16:07:34 +02:00
18009303ae
instanciate device or host controller
2014-09-24 14:00:00 +02:00
60324295fa
manage clock domain crossing and data width conversion in gtx
2014-09-24 13:56:12 +02:00
f436069a04
create sata clock (sata_tx/2 for a 32 bits data path)
2014-09-24 13:55:06 +02:00
7790105913
realign rxdata / rxcharisk directly in gtx
2014-09-24 12:13:43 +02:00
f74471d027
add device ctrl skeleton (we will use it for simulation with the host)
2014-09-24 11:37:28 +02:00
d78cae1b57
more ctrl skeleton
2014-09-24 11:07:36 +02:00
71bfd036d0
add ctrl skeleton
2014-09-24 00:01:01 +02:00
fa509b3365
rearrange code and remove datapath for now
2014-09-23 23:03:32 +02:00
22ea5b08b0
clean up and add K7SATAGTXReconfig skeleton (empty but we don't need it for now)
2014-09-23 22:40:01 +02:00
674e0b3581
remove GTXE2_COMMON (we use in fact CPLL and not QPLL, GTXE2_COMMON was here in design just because of an old ISE bug)
...
(see http://www.xilinx.com/support/answers/45410.html for more information)
2014-09-23 22:17:08 +02:00
e0fd313ce0
add data path from another design (need to be adapted to SATA specification)
2014-09-23 17:36:11 +02:00
Florent Kermarrec
Sebastien Bourdeauducq