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7 Commits

Author SHA1 Message Date
George Hilliard 8954041a93 clock/lattice_ecp5/ECP5PLL: Only consider non-dpa clocks as feedback 
Dynamically adjusting the phase of a feedback will cause it to unlock.
The phase adjust ports are shared by all the outputs, so there is no
technical way to prevent this.  Allow the user to indicate that they
will not adjust a clock when requesting an output by setting
uses_dpa=False, and only consider those that the user has promised not
to use.
 2021-07-08 08:14:14 -05:00
Florent Kermarrec cecb36d608 test/test_clock: update with new supported devices. 2020-11-09 10:37:20 +01:00
Florent Kermarrec f7b6dd05ae cores/clock: add initial Xilinx Ultrascale Plus PLL/MMCM/IDELAYCTRL support. 2020-09-03 18:58:10 +02:00
Florent Kermarrec 77ae243310 test: add SPDX License identifier to header and specify file is part of LiteX. 2020-08-23 15:40:21 +02:00
Florent Kermarrec 383fcd36d6 soc/cores/clock: add CycloneVPLL. 2020-04-07 17:24:12 +02:00
Florent Kermarrec 0f17547c5b soc/cores/clock: add initial AlteraClocking/CycloneIV support. 2020-04-07 16:59:53 +02:00
Florent Kermarrec eb9f54b2bc test: add initial (minimal) test for clock abstraction modules. 
Also fix divclk_divide_range on S6DCM.
 2020-03-13 12:38:23 +01:00