22 Commits

Author	SHA1	Message	Date
Sebastien Bourdeauducq	019ef16db4	fhdl: remove broken fragment iadd	2011-12-11 01:10:59 +01:00
Sebastien Bourdeauducq	b00581616e	convtools: insert reset on variables	2011-12-11 01:10:37 +01:00
Sebastien Bourdeauducq	d3127fd5d8	autofragment: remove debug	2011-12-10 20:48:23 +01:00
Sebastien Bourdeauducq	44f44b8a05	fhdl: autofragment	2011-12-10 20:47:21 +01:00
Sebastien Bourdeauducq	4b15a84505	fhdl: fix += for empty fragment	2011-12-10 20:47:06 +01:00
Sebastien Bourdeauducq	a49ecc4331	fhdl: pad support in fragments	2011-12-10 20:25:24 +01:00
Sebastien Bourdeauducq	fa63cc1ec8	fhdl: replication support	2011-12-09 13:11:34 +01:00
Sebastien Bourdeauducq	b0c5b74c22	verilog: handle default in case statements	2011-12-08 23:04:20 +01:00
Sebastien Bourdeauducq	512655c108	fhdl: improve automatic signal naming	2011-12-08 21:28:20 +01:00
Sebastien Bourdeauducq	84eb964adc	fhdl: support negation operator	2011-12-08 21:15:44 +01:00
Sebastien Bourdeauducq	bf021efa2b	verilog: fix unary operator conversion	2011-12-08 21:15:24 +01:00
Sebastien Bourdeauducq	ed05ec5f6a	instances: signal override	2011-12-08 18:56:14 +01:00
Sebastien Bourdeauducq	a6b86168ce	Simple bus base class	2011-12-08 18:47:32 +01:00
Sebastien Bourdeauducq	1b637cea61	Instance support	2011-12-08 16:35:32 +01:00
Sebastien Bourdeauducq	fab02f84cb	fhdl: fix implicit slice index	2011-12-07 22:21:30 +01:00
Sebastien Bourdeauducq	82f77180d5	fhdl: cleanup value bv	2011-12-07 22:21:10 +01:00
Sebastien Bourdeauducq	0e8d894a35	Variable conversion	2011-12-05 22:00:06 +01:00
Sebastien Bourdeauducq	4340680704	Cleanup	2011-12-05 19:25:32 +01:00
Sebastien Bourdeauducq	ec51f09c98	Case support + register bank generator	2011-12-05 17:43:56 +01:00
Sebastien Bourdeauducq	e099f4d52f	Reset insertion	2011-12-04 22:41:50 +01:00
Sebastien Bourdeauducq	cd8544c758	Verilog generator	2011-12-04 22:26:32 +01:00
Sebastien Bourdeauducq	499b95a519	Initial import, FHDL basic structure, divider example	2011-12-04 16:44:38 +01:00