f6d6611a81
software/liblitedram: Introduce SDRAM_PHY_DELAY_JUMP and set to 4 on 7-Series instead of 1 to improve calibration robustness on some boards.
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This is for example required on the STLV7325 board.
2022-02-24 17:32:58 +01:00
82daa48e09
software/bios/libbase: Always do memtest/memspeed when main_ram is present.
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- Enable memtest/memspeed on design with HyperRAM.
- Allow comparisons between SDRAM/HyperRAM and integrated RAM.
2022-02-23 10:19:20 +01:00
4acbafbc19
cpu/naxriscv allow reset_vector >= 0x80000000
2022-02-22 12:21:05 +01:00
038b66bae5
cpu/naxriscv add reset vector support
2022-02-22 11:06:02 +01:00
cd57202e5e
cpu/NaxRiscv fix for windows
2022-02-22 10:37:22 +01:00
1b62f14230
build: Add initial OpenFPGA build backend with SOFA support and minimal blinky example.
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OpenFPGA should be installed by following installation steps from https://github.com/lnis-uofu/OpenFPGA .
SOFA can be cloned from https://github.com/lnis-uofu/SOFA
Environment variables then need to be set:
export LITEX_ENV_OPENFPGA=/PATH_TO_OPENFPGA
export LITEX_ENV_OPENFPGA_SOFA=/PATH_TO_SOFA
A simple blinky test design is provided and can be built by executing blinky.py.
2022-02-21 17:07:39 +01:00
8559b88ad8
build/efinix/platform: Transform Slices until we get target Signal (fixes SDCard SD-mode on TI62-F225).
2022-02-21 10:34:09 +01:00
d2a2c2e5dc
cpu/naxriscv update nax
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fix sbt version
2022-02-20 22:31:04 +01:00
9d68a9479c
Merge pull request #1153 from fjullien/allow_module_in_project_dir
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sim: allow custom modules to be in custom path
2022-02-18 17:16:25 +01:00
fde7fc87a3
Merge pull request #1214 from Dolu1990/memspeed
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Improve bios memspeed performances
2022-02-18 16:30:30 +01:00
ea6cadf7b2
bios/memtest fix tabulations
2022-02-18 13:23:10 +01:00
eccd64348d
bios/memtest improve memspeed performances
2022-02-18 13:21:05 +01:00
3510daaf0c
clock/efinix/create_clkout: Set with_reset to True by default (similar to others vendors).
2022-02-18 12:10:43 +01:00
6049018f10
cpu/naxriscv fix boot-helper.S
2022-02-18 11:54:47 +01:00
6ce737956b
cpu/naxriscv: Switch to 64-bit RAM data-width.
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Also make sure to do a git pull before the git checkout to get updated commits.
2022-02-18 11:46:11 +01:00
55d9b3a403
soc/add_sdram: Introduce data_width_ratio and fix id_width in UpConvert case.
2022-02-18 11:34:08 +01:00
51d952c2d3
interconnect/axi: Simplify/Fix AXIUpConverter.
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Assume size of "axi_from" burst >= "axi_to" data_width.
2022-02-18 11:33:28 +01:00
8dbb572b7a
cpu/naxriscv: Prepare for data_width conversion in LiteX (not yet enabled).
2022-02-17 18:36:42 +01:00
6788f3b9cb
cpu/naxriscv/core: Uncomment git_setup and update sha1.
2022-02-17 17:51:40 +01:00
52ed20178c
Merge pull request #1213 from Dolu1990/naxriscv
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cpu/naxriscv Add pythondata support
2022-02-17 17:32:00 +01:00
1052584cf7
integration/soc/add_sdram: Use new AXIUpConverter when up-converting is required (Instead of going through Wishbone).
2022-02-17 17:23:16 +01:00
ea49be9302
interconnect/axi: Add initial AXIUpConverter (for use with NaxRiscv/LiteDRAM).
2022-02-17 17:22:30 +01:00
f62eca77e3
test/test_axi: Minor cleanups.
2022-02-17 15:13:05 +01:00
a3243e32ec
cpu/naxriscv Add pythondata support
2022-02-17 14:59:56 +01:00
d0dc5c8d95
CHANGES: Update.
2022-02-17 10:36:05 +01:00
c494ea231b
cpu: Add initial NaxRiscv support (From out of tree prototyping in litex_naxriscv_test).
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- Supporting rv32ima for now.
- No interrupt support yet.
- AXI4 direct interfaces to LiteDRAM (fixed at 128-bit for now).
- AXI4-Lite interfaces to LiteX main bus.
- Pre-generated netlist used for now (need to allow customization/re-generation).
- Running in simulation with: litex_sim --cpu-type=naxriscv
- Running on hardware with: python3 -m litex_boards.targets.digilent_arty --cpu-type=naxriscv --build --load
Demo with Linux and Doom on SDS1104X-E scope:
https://twitter.com/enjoy_digital/status/1493996880593887235
2022-02-17 10:28:48 +01:00
38a047bed1
cpu: Add initial NEORV32 support (From out of tree prototyping in litex_neorv32_test repo).
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- Only configured for rv32i for now (need to create variants).
- I/DBus interfaces probably not optimal (latency).
- Converted from VHDL to Verilog through GHDL-Yosys-Synth (should also support direct VHDL use with toolchains supporting it).
- Interrupt not yet implemented.
- Running in simulation with litex_sim --cpu-type=neorv32.
- Running on Arty with: python3 -m litex_boards.targets.digilent_arty --cpu-type=neorv32 --build --load:
__ _ __ _ __
/ / (_) /____ | |/_/
/ /__/ / __/ -_)> <
/____/_/\__/\__/_/|_|
Build your hardware, easily!
(c) Copyright 2012-2022 Enjoy-Digital
(c) Copyright 2007-2015 M-Labs
BIOS built on Feb 14 2022 16:10:24
BIOS CRC passed (83edf3c3)
Migen git sha1: ac70301
LiteX git sha1: 0d218306
2022-02-17 09:59:30 +01:00
d37ef60e70
remote/comm_udp: Increase timeout.
2022-02-16 17:57:24 +01:00
edf65107fb
libliteeth/tftp: Implement blocksize support (RFC2348) and increase blocksize from 512 bytes to 1024 bytes (mechanically increase filesize limitation from 32MB to 64MB).
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See https://datatracker.ietf.org/doc/html/rfc2348 .
2022-02-16 16:46:26 +01:00
f46d1c190b
cpu/integration: Fix csr_decode.
2022-02-15 22:17:45 +01:00
9f2ffbb7ef
Merge pull request #1208 from trabucayre/cpu_fix_csr_decoding
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Cpu fix csr decoding
2022-02-15 22:05:51 +01:00
855bc26f16
litex_setup/cv32e41p: Only install it with full config.
2022-02-15 09:45:23 +01:00
2993928b31
Merge pull request #1207 from pcotret/cv32e41p_support
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Add support for the CV32E41P RISC-V CPU
2022-02-15 09:43:03 +01:00
de6238e7c0
Merge pull request #1201 from shenki/microwatt-countzero
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microwatt: Move to latest and add countzero module
2022-02-15 09:36:43 +01:00
0427006663
soc/cores/cpu: eos, zynq7000 & zynqmp: don't decode CSR address
2022-02-15 07:32:26 +01:00
af69c572d8
litex/soc/integration/soc: SocRegion: allows to bypass decoding; SoC: add attribute to bypass CSR decoding
2022-02-15 07:31:19 +01:00
d4448827ac
add cv32e41p
2022-02-14 22:43:34 +01:00
d506b4418e
add isr support for cv32e41p
2022-02-14 22:09:46 +01:00
86373605ce
add pythondata for cv32e41p
2022-02-14 22:06:25 +01:00
0d2183062d
cpu/serv: Remove duplicated separator.
2022-02-14 11:52:29 +01:00
f91941731a
build/xilinx/platform: Add specialized add_platform_command to handle yosys+nextpnr specificities.
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Also remove symbiflow+nextpnr commented flow.
2022-02-14 10:44:13 +01:00
378c430dd0
soc/add_sdram: Fix typo when removing Rocket specific hardcoding.
2022-02-12 21:47:08 +01:00
dff33885de
cpu/zynqmp: Use dict for fpd/lpd selection.
2022-02-09 16:03:53 +01:00
80fd8e26a7
Merge pull request #1203 from trabucayre/zynqmp_complete_axi
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zynqmp/core: allows users to select data_size and interface id
2022-02-09 15:46:46 +01:00
b0d9223b78
zynqmp/core: allows users to select data_size and interface id
2022-02-09 07:03:44 +01:00
ad78965f41
soc/add_sdram/axi: Avoid some Rocket specific hardcoding (to use it on other CPUs).
2022-02-08 18:30:55 +01:00
7cc781f7be
cpu/zynq7000: Add Ilia to copyrights.
2022-02-07 07:57:59 +01:00
b749b3acb7
cpu/zynqmp: Add missing header/copyrights.
2022-02-07 07:57:29 +01:00
bd3d063d87
Merge pull request #1199 from sergachev/feature/zynqmp
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cores/cpu: add ZynqMP (UltraScale+ MPSoC) support
2022-02-07 07:53:25 +01:00
420934e206
microwatt: Move to latest and add countzero module
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Mcrowatt has renamed countbits to countzero. Update to the latest and
update the file list.
Signed-off-by: Joel Stanley <joel@jms.id.au>
2022-02-07 12:22:11 +10:30
Florent Kermarrec
Dolu1990
Gwenhael Goavec-Merou
Pascal Cotret
Joel Stanley