Sebastien Bourdeauducq
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797411c1a9
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generic_platform: do not create clock domains during Verilog conversion
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2013-03-18 18:44:58 +01:00 |
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Sebastien Bourdeauducq
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6feb6e60b0
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New clock_domain API
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2013-03-15 18:46:11 +01:00 |
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Sebastien Bourdeauducq
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c06a821452
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generic_platform: implicit get_fragment
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2013-03-12 16:14:13 +01:00 |
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Sebastien Bourdeauducq
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ef833422c7
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generic_platform/get_verilog: pass additional args to verilog.convert
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2013-02-23 19:42:29 +01:00 |
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Sebastien Bourdeauducq
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0321513726
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corelogic -> genlib
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2013-02-23 19:37:27 +01:00 |
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Sebastien Bourdeauducq
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44ae20d3c4
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generic_platform: prefix subsignals
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2013-02-20 18:27:04 +01:00 |
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Sebastien Bourdeauducq
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38c3566717
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generic_platform: add name
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2013-02-14 20:02:35 +01:00 |
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Sebastien Bourdeauducq
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ed4d65f2be
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generic_platform: fix IO signal set when using existing record objects
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2013-02-13 23:29:33 +01:00 |
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Sebastien Bourdeauducq
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feec035cc8
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generic_platform: get absolute path for added sources
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2013-02-12 19:16:00 +01:00 |
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Sebastien Bourdeauducq
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709845e618
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generic_platform: fix request
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2013-02-11 17:54:01 +01:00 |
|
Sebastien Bourdeauducq
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f13ad035e1
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Support for command line arguments
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2013-02-08 22:23:58 +01:00 |
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Sebastien Bourdeauducq
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7b8e8a19f3
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Support adding Verilog/VHDL files
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2013-02-08 20:25:20 +01:00 |
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Sebastien Bourdeauducq
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32dcfc6d02
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generic_platform: support name remapping
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2013-02-08 18:27:46 +01:00 |
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Sebastien Bourdeauducq
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fef9d0fc78
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generic_platform: fix typo
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2013-02-08 17:43:04 +01:00 |
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Sebastien Bourdeauducq
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fb5130fc1f
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Initial version
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2013-02-07 22:07:30 +01:00 |