27d87c9412
fhdl/structure: disable we_granularity when larger than width
2012-11-23 23:08:12 +01:00
d2c61e6a90
sim/generic/multiread: do not return spurious items
2012-11-23 23:07:25 +01:00
74721b206f
pytholite: fix import of _Slice
2012-11-23 21:20:18 +01:00
95122bb778
pytholite/io: support memory
2012-11-23 20:36:09 +01:00
f42683b71e
fhdl/structure/Memory: fix we width
2012-11-23 19:21:52 +01:00
784a399431
examples/memory: use new get_port API
2012-11-23 19:18:08 +01:00
0f6215a13a
fhdl/structure: add Memory.get_port API
2012-11-23 19:17:49 +01:00
9d3e218863
fhdl: use object creation counter (HUID) as hash. This finally makes the generated code textually the same across runs.
2012-11-23 18:38:03 +01:00
3971600917
fhdl/structure: use sets for memories and instance collections
2012-11-23 17:20:08 +01:00
7c6ebcf753
examples/pytholite/uio: demonstrate memories
2012-11-23 16:24:20 +01:00
f3efd74dfd
uio: support memories
2012-11-23 16:23:24 +01:00
ab31b4d99c
bus: memory initiator
2012-11-23 16:22:50 +01:00
0b7dd7bdce
pytholite/io: fix Wishbone writes + support sel attribute
2012-11-23 13:40:46 +01:00
20d87682ad
examples/pytholite/uio: simulate and convert Pytholite
2012-11-23 13:10:40 +01:00
4c216d8f11
pytholite/io: support Wishbone reads
2012-11-23 13:09:55 +01:00
0b24a2ff36
pytholite/io: support Wishbone writes
2012-11-23 12:41:50 +01:00
f098c5c695
pytholite/compiler: pass keyword arguments to gen_io
2012-11-23 12:40:57 +01:00
51e2e6ecd0
fhdl/verilog: remove empty cases
2012-11-18 16:32:51 +01:00
89643bc434
sim/ipc/Message: convert values
2012-11-17 23:19:40 +01:00
e92af9de59
pytholite/transel: use python3-compatible comparison methods
2012-11-17 23:16:07 +01:00
6434ddd95a
examples/pytholite: add uio example
2012-11-17 22:26:14 +01:00
b6b4c5d70e
uio/ioo: fix UnifiedIOSimulation
2012-11-17 22:25:42 +01:00
1cabcb3c3f
uio: support generator trampolining in simulation
2012-11-17 19:59:22 +01:00
be68ecfc72
uio: add simulation I/O object
2012-11-17 19:55:33 +01:00
7add4c6f3c
uio: unified I/O object
2012-11-17 19:54:50 +01:00
d10df1a8ab
actorlib/sim: swap TokenExchanger parameters
2012-11-17 19:46:28 +01:00
d4baac6c0f
bus/csr: allow specifying existing interface
2012-11-17 19:44:25 +01:00
5ae1b2644e
tb/asmicon: new initiator API
2012-11-17 19:43:30 +01:00
86090e1cbd
bus/asmibus: swap port position to be consistent with wishbone API
2012-11-17 19:42:39 +01:00
ece786d6aa
bus/wishbone: allow specifying existing interface
2012-11-17 19:42:06 +01:00
d0d4c48098
bus/transactions: add busname parameter
2012-11-17 19:36:08 +01:00
897a2e3f9c
actorlib/sim: split TokenExchanger
2012-11-17 14:15:51 +01:00
eb156af20c
pytholite/io: support token pull
2012-11-16 23:48:41 +01:00
748741b49a
examples/pytholite/basic: demonstrate conversion to Verilog
2012-11-16 19:38:57 +01:00
7c7addbbe8
examples: basic Pytholite demo
2012-11-16 19:34:34 +01:00
dd9a102a78
pytholite/io: support token push
2012-11-16 19:24:45 +01:00
a0ff666628
lm32: replace $clog2 with macro
...
Unfortunately, XST does not support $clog2 with the localparam keyword
(the parameter keyword works just fine). Define a macro which replaces the
call with a constant function.
This commit can be reverted if the bug in XST is fixed.
Signed-off-by: Michael Walle <michael@walle.cc>
2012-11-14 14:30:16 +01:00
d15d982904
lm32: split lm32_include.v
2012-11-14 14:25:15 +01:00
2ae17af75b
lm32: fix documentation style
...
Signed-off-by: Michael Walle <michael@walle.cc>
2012-11-14 14:09:21 +01:00
4bee685c54
lm32: remove unneeded parameter in lm32_dp_ram
...
addr_depth can be computed by addr_width.
Signed-off-by: Michael Walle <michael@walle.cc>
2012-11-14 14:08:41 +01:00
10495e72d0
lm32: rename mem array in lm32_dp_ram
...
Be compatible with original proprietary DP RAM instantiation. This is
needed for simulation, where r0 is initialized to zero in lm32_cpu.v.
Signed-off-by: Michael Walle <michael@walle.cc>
2012-11-14 14:08:06 +01:00
47baad4fe1
lm32: replace clogb2 by builtin $clog2
...
This function is fixed in ISE since version 14.1 (see AR #44586 ). If the
builtin function is used, the design can be simulated with Icarus Verilog.
Signed-off-by: Michael Walle <michael@walle.cc>
2012-11-14 14:07:28 +01:00
bf5ce8dc20
pytholite: move expression and register handling to separate modules
2012-11-11 23:48:23 +01:00
f59fd69e34
pytholite/compiler: recognize composite I/O pattern
2012-11-11 18:03:16 +01:00
0b5652bb79
pytholite/compiler: visit_assign_special
2012-11-11 15:52:06 +01:00
687d18a150
pytholite: move FSM management to separate module
2012-11-11 14:30:25 +01:00
409a5570e4
pytholite/compiler: refactor visit_block
2012-11-11 14:17:52 +01:00
fb63698ef4
pytholite/compiler: clean up visit_statement
2012-11-10 23:30:14 +01:00
6ebd1e4503
pytholite: forward 'yield call' statements to io module
2012-11-10 22:59:14 +01:00
48acb1bcfd
pytholite: introduce io module
2012-11-10 21:51:19 +01:00
Sebastien Bourdeauducq
Michael Walle