2bb9c6b649
add verilog backend to use the core with a "standard" flow
2015-01-19 20:38:48 +01:00
6de7e15a0c
refactor code
2015-01-17 13:22:52 +01:00
1170a1070b
add need_reset from controller to request system reset when SATA is not locked
2015-01-15 00:56:47 +01:00
d196a517d6
use 166MHz clock
2015-01-08 22:58:26 +01:00
7df1d75dee
use max_count of 16 and clean up
2014-12-23 23:19:48 +01:00
0f8f89a269
update clock constraints for SATA1 and use sys_clk of 200MHz
...
- data seems stable (mila capture) except when receive the ALIGN primtive from the device, we should maybe disable alignment on the HOST when link is ready...
2014-12-17 19:24:23 +01:00
37fe17debe
use Vivado programmer instead of IMPACT
2014-12-17 12:07:11 +01:00
3f7406a937
various fixes and simplifications, SATA1 & SATA2 OK
2014-10-28 02:15:19 +01:00
e2cbb3a048
platforms: merge but keep support for iMPACT for now (xc3sprog need to be tested on Windows)
2014-10-24 12:32:08 +02:00
bc5b23b808
use SGMII clk (125MHz) and SFP for test on KC705
2014-09-30 09:07:15 +02:00
1d053bd7ee
modify TestDesign to be able to simulate phy with host <--> device loopback
2014-09-25 15:37:49 +02:00
435bc22fa0
integrate phy in test design and start fix syntax errors
2014-09-24 16:07:34 +02:00
7e31ef2152
init with repo with simple TestDesign
2014-09-22 13:36:43 +02:00
Florent Kermarrec