14 commits

Author	SHA1	Message	Date
Sebastien Bourdeauducq	a67b4baa0c	sim: VCD output support	2015-09-21 21:20:31 +08:00
Sebastien Bourdeauducq	7f767095ec	sim: support generators yielding statements	2015-09-20 15:04:15 +08:00
Sebastien Bourdeauducq	320dffb4ac	sim: memory access from generators	2015-09-20 14:52:26 +08:00
Sebastien Bourdeauducq	336728413a	simplify imports, migen.fhdl.std -> migen	2015-09-12 19:34:07 +08:00
Florent Kermarrec	1051878f4c	global: pep8 (E302)	2015-04-13 20:45:35 +02:00
Florent Kermarrec	17e5249be0	global: pep8 (replace tabs with spaces)	2015-04-13 20:07:07 +02:00
Florent Kermarrec	dbaeaf7833	remove trailing whitespaces	2014-10-17 17:08:46 +08:00
Sebastien Bourdeauducq	63c1d7e4b7	New simulation API	2014-01-26 22:19:43 +01:00
Sebastien Bourdeauducq	83e2b0243d	examples: remove direct uses of Fragment	2013-07-24 18:47:25 +02:00
Sebastien Bourdeauducq	70ffe86356	New migen.fhdl.std to simplify imports + len->flen	2013-05-22 17:11:09 +02:00
Sebastien Bourdeauducq	49cfba50fa	New 'specials' API	2013-02-22 17:56:35 +01:00
Sebastien Bourdeauducq	92b67df41c	sim: default runner to Icarus Verilog	2013-02-09 17:04:53 +01:00
Sebastien Bourdeauducq	2418367c7a	examples/sim/memory: do not use MemoryPort	2012-11-26 18:19:10 +01:00
Sebastien Bourdeauducq	973c00938d	Reorganize examples folder	2012-06-12 17:49:50 +02:00

Renamed from examples/memory_sim.py (Browse further)