Sebastien Bourdeauducq
|
8ae3a00a94
|
gensoc: simplify WB address decoding
|
2014-11-30 22:05:51 +08:00 |
|
Sebastien Bourdeauducq
|
4189440eef
|
minicon: small simplifications
|
2014-11-28 08:28:39 +08:00 |
Yann Sionneau
|
edb1622668
|
spiflash: BB write support
|
2014-11-27 23:10:39 +08:00 |
|
Sebastien Bourdeauducq
|
bab6bb7c4a
|
gensoc: fix align
|
2014-11-27 23:05:36 +08:00 |
|
Sebastien Bourdeauducq
|
2cd80990e4
|
minicon: fix use of phy phases
|
2014-11-27 22:13:17 +08:00 |
|
Sebastien Bourdeauducq
|
8418ccafdc
|
minicon: remove unused signals and fix indent
|
2014-11-27 22:12:05 +08:00 |
|
Yann Sionneau
|
cf92821fcf
|
Refactor directory hierarchy of sdram phys and controllers
|
2014-11-27 22:09:10 +08:00 |
|
Yann Sionneau
|
f33b285af1
|
Minicon: small SDRAM controller
|
2014-11-27 22:09:03 +08:00 |
Florent Kermarrec
|
5202f89db1
|
ethmac/last_be: remove fake signal (fixed in Migen)
|
2014-11-21 14:48:17 -08:00 |
|
Sebastien Bourdeauducq
|
b7028848b2
|
ethmac: use new EndpointDescription API
|
2014-11-20 22:32:32 -08:00 |
|
Sebastien Bourdeauducq
|
33530e0921
|
ethmac: style/renaming
|
2014-11-20 18:01:48 -08:00 |
|
Florent Kermarec
|
603c2641bb
|
new Ethernet MAC
|
2014-11-20 16:47:22 -08:00 |
|
Florent Kermarrec
|
8e4b89849c
|
use new direct access on endpoints
|
2014-10-20 23:13:37 +08:00 |
|
Florent Kermarrec
|
34ed315a48
|
remove trailing whitespaces
|
2014-10-17 17:14:40 +08:00 |
|
Sebastien Bourdeauducq
|
e53fb88b85
|
uart: minor cleanup and fix
|
2014-10-10 15:33:27 +08:00 |
|
Florent Kermarrec
|
5e5f436aa6
|
uart: split it and use dataflow
This make the code easier to understand and allow the reuse of UARTRX & UARTTX
on designs without CPU (e.g miscope).
|
2014-10-10 15:24:47 +08:00 |
|
Florent Kermarrec
|
c0c17030fd
|
spi_flash: simplify usage by removing cmd, cmd_width, addr_width parameters
|
2014-09-04 15:23:39 +08:00 |
|
Sebastien Bourdeauducq
|
36434b62f0
|
sdram: merge DFII_PIX_RDDATA_SIZE and DFII_PIX_WRDATA_SIZE
|
2014-09-03 15:02:38 +08:00 |
|
Sebastien Bourdeauducq
|
a7b4550e59
|
sdramphy/initsequence: cleanup and expose DDR3 MR1 value
|
2014-09-03 14:21:30 +08:00 |
|
Florent Kermarrec
|
114890ee80
|
sdramphy/initsequence: clean up mr1/mr2 computation on DDR3 and enable Dynamic ODT
|
2014-09-02 10:54:29 +08:00 |
|
Sebastien Bourdeauducq
|
2234f50223
|
k7ddrphy: add bitslip control for incoming DQ
|
2014-09-01 19:54:39 +08:00 |
|
Sebastien Bourdeauducq
|
5483b37c8f
|
k7ddrphy: write leveling and read calibration support
|
2014-08-31 21:54:28 +08:00 |
|
Sebastien Bourdeauducq
|
19abe2b888
|
k7ddrphy: do not register T at SERDES (fixes timing problem)
|
2014-08-31 21:53:35 +08:00 |
|
Sebastien Bourdeauducq
|
541e5abbc7
|
k7ddrphy: update comment
|
2014-08-22 19:02:57 +08:00 |
|
Sebastien Bourdeauducq
|
66fe45ba96
|
k7ddrphy: decrease CAS latency to account for cmd/data flight time
|
2014-08-22 18:46:01 +08:00 |
|
Sebastien Bourdeauducq
|
b94647ab16
|
k7ddrphy: suppress idiotic bitgen warning about ISERDES IOBDELAY parameter
|
2014-08-22 18:45:25 +08:00 |
|
Florent Kermarrec
|
1c381acc6f
|
k7ddrphy: fix read_latency (CL is 2 sys_clk since we use quarter rate)
|
2014-08-14 22:46:06 +08:00 |
|
Florent Kermarrec
|
acbba37f5f
|
k7ddrphy: set bitslip to 0 on ISERDESE2 (needed at least for sim)
|
2014-08-14 22:46:06 +08:00 |
|
Florent Kermarrec
|
2e4bfe154f
|
k7ddrphy: add ODELAYE2 on dm path to match dq path (ODELAYE2 even configure with a delay of 0 generates a delay)
|
2014-08-14 22:46:06 +08:00 |
|
Florent Kermarrec
|
bb85f29f91
|
k7ddrphy: fix write_latency and take care of OSERDESE2 latency on oe
|
2014-08-14 22:46:06 +08:00 |
|
Florent Kermarrec
|
85b29c883a
|
sdramphy/initsequence: fix and add format_mr0 function
|
2014-08-14 14:17:54 +08:00 |
|
Florent Kermarrec
|
9844c25df9
|
k7ddrphy: add SERDES reset
|
2014-08-14 14:16:41 +08:00 |
|
Florent Kermarrec
|
194a5a0491
|
lasmicon: fix reset_n level
|
2014-08-14 14:15:48 +08:00 |
|
Sebastien Bourdeauducq
|
c8dd4d2b40
|
k7ddrphy: send rddata_valid on all phases
|
2014-08-09 11:00:13 +08:00 |
|
Sebastien Bourdeauducq
|
8deadc5760
|
dfii: drive ODT and RESET_N
|
2014-08-08 21:56:35 +08:00 |
|
Sebastien Bourdeauducq
|
1322c0484b
|
lasmicon: drive ODT and RESET_N
|
2014-08-08 21:55:34 +08:00 |
|
Sebastien Bourdeauducq
|
0550cbb3ce
|
lasmicon: add CWL to PHY settings
|
2014-08-08 21:55:12 +08:00 |
|
Sebastien Bourdeauducq
|
777ebb7875
|
sdramphy/gensdrphy: fix rddata_en generation
|
2014-08-08 21:41:07 +08:00 |
|
Sebastien Bourdeauducq
|
a2c7ff4c0c
|
sdramphy: initial K7 DDR3 support
|
2014-08-08 21:28:26 +08:00 |
|
Florent Kermarrec
|
293ac09673
|
sdramphy/bios: make sdrrd/sdrwr generic
|
2014-08-08 19:25:10 +08:00 |
|
Sebastien Bourdeauducq
|
cfc37a3fa5
|
sdramphy/initsequence: rewrite DDR3 initialization sequence
|
2014-08-08 19:15:05 +08:00 |
|
Sebastien Bourdeauducq
|
e8db842538
|
s6ddrphy: fix DFI interface data width computation
|
2014-08-08 19:14:15 +08:00 |
|
Sebastien Bourdeauducq
|
efb2466c7e
|
gensoc: add id for KC705
|
2014-08-06 23:53:51 +08:00 |
|
Florent Kermarrec
|
d1ff43faa7
|
gensoc/cpuif: do not generate access functions for registers > 64 bits
|
2014-08-04 22:38:19 +08:00 |
|
Sebastien Bourdeauducq
|
213cb43ae5
|
Keep only basic SoC designs in MiSoC
|
2014-08-03 12:30:15 +08:00 |
|
Florent Kermarrec
|
25b3aff6f1
|
sdramphy: add init sequence for DDR3
|
2014-07-31 10:29:32 +08:00 |
|
Yann Sionneau
|
32171da46d
|
Better UART baudrate generator, and testbench
This enables high speed (tested to 4Mbps) operation.
|
2014-07-31 10:24:52 +08:00 |
|
Florent Kermarrec
|
d4833cb3dc
|
cpuif: remove limitations on csr data_width
|
2014-06-28 17:39:55 +02:00 |
Robert Jordens
|
81ed92d3b9
|
spiflash: redundant slice
|
2014-05-24 10:39:07 +02:00 |
|
Florent Kermarrec
|
f4c0648289
|
gensdrphy: fix dm generation
|
2014-05-21 21:16:06 +02:00 |