8fd092ca12
crg: support VGA pixel clock reprogramming
2013-03-28 19:07:17 +01:00
fdf7f10f54
Automatically build CSR access functions
2013-03-25 14:42:48 +01:00
6010308317
software/videomixer: report char position + detected resolution, detect phase at beginning
2013-03-24 00:46:23 +01:00
d65941d6cc
dvisampler: channel synchronization
2013-03-22 18:37:10 +01:00
515cdb2bd8
dvisampler: character synchronization
2013-03-21 22:56:13 +01:00
2315544b36
software/videomixer: quick hack for phase detection
2013-03-21 15:32:26 +01:00
a9b723568a
Use new module, autoreg and eventmanager Migen APIs
2013-03-10 19:32:38 +01:00
dd6eacba62
Remove uses of the RE signal on field registers
2012-10-09 19:08:37 +02:00
674b3f1a8c
software/include/hw: add flash offset for filesystem
2012-06-02 23:44:57 +02:00
3a4408a880
software: merge flash.h into mem.h
2012-05-31 16:30:30 +02:00
22f7d1716e
Remove some boilerplate
2012-05-24 19:22:27 +02:00
f6f42293d1
Clock frequency detection
2012-05-22 13:23:44 +02:00
4d754dbb33
bios: serial, network and flash boot support
2012-05-21 22:57:12 +02:00
275ed9cd9c
bios: timer support
2012-05-21 22:56:21 +02:00
c01594f9fd
Common interrupt numbers
2012-05-21 19:52:41 +02:00
79124d822b
Identifier
2012-05-17 01:41:41 +02:00
bb798176fc
Common include files
2012-05-16 10:20:04 +02:00
b6aa40d845
bios: automatically enable hardware memory controller and test memory
2012-05-15 19:29:26 +02:00
92ac69bae3
dfii: new design
2012-02-23 21:21:07 +01:00
f35cd4a85b
Prepare for new DDR PHY
2012-02-19 18:43:42 +01:00
5bc840b9c1
DFI injector (untested)
2012-02-17 23:50:10 +01:00
c387ce7ce5
Map DDR PHY controls in CSR
2012-02-17 17:34:59 +01:00
5cde57cb65
software: use new UART
2012-02-06 17:53:41 +01:00
e2317bc83b
flash: remove splash screens
2012-02-05 19:12:33 +01:00
1a4a6eb445
Copy some software code from the original Milkymist SoC.
...
Libbase should keep its RAM usage to a minimum as it is meant to
be executed before the SDRAM is up and running. (Having lots of
code is OK though as we XIP from the flash)
2012-02-03 12:08:17 +01:00
Sebastien Bourdeauducq