Nina Engelhardt
|
4ebbfa63bf
|
add mist synthesis mode to build
|
2013-08-12 13:13:25 +02:00 |
Nina Engelhardt
|
6e64016885
|
add edif build routines
|
2013-08-03 10:55:12 +02:00 |
Sebastien Bourdeauducq
|
f7f19b78e4
|
Fragment -> _Fragment
|
2013-07-26 15:13:24 +02:00 |
|
Sebastien Bourdeauducq
|
05bc2885e9
|
Call finalize() after CRG creation
|
2013-07-04 19:49:39 +02:00 |
Robert Jordens
|
e233c62d27
|
* generic_platform.py: add a finalize() method
... to add e.g. timing constraints after the other modules have
had their say and when the signal names are known
|
2013-06-27 19:17:02 +02:00 |
|
Sebastien Bourdeauducq
|
6b56428a21
|
Shorter multipin signal definition
|
2013-06-25 22:57:31 +02:00 |
|
Sebastien Bourdeauducq
|
759858f739
|
Use migen.fhdl.std
|
2013-05-26 18:07:26 +02:00 |
|
Sebastien Bourdeauducq
|
3b19dfc412
|
Support for platform info
|
2013-03-26 19:17:35 +01:00 |
|
Sebastien Bourdeauducq
|
74cc4d22cd
|
generic_platform: remove obj in request + add lookup_request
|
2013-03-26 17:56:53 +01:00 |
|
Sebastien Bourdeauducq
|
797411c1a9
|
generic_platform: do not create clock domains during Verilog conversion
|
2013-03-18 18:44:58 +01:00 |
|
Sebastien Bourdeauducq
|
6feb6e60b0
|
New clock_domain API
|
2013-03-15 18:46:11 +01:00 |
|
Sebastien Bourdeauducq
|
c06a821452
|
generic_platform: implicit get_fragment
|
2013-03-12 16:14:13 +01:00 |
|
Sebastien Bourdeauducq
|
ef833422c7
|
generic_platform/get_verilog: pass additional args to verilog.convert
|
2013-02-23 19:42:29 +01:00 |
|
Sebastien Bourdeauducq
|
0321513726
|
corelogic -> genlib
|
2013-02-23 19:37:27 +01:00 |
|
Sebastien Bourdeauducq
|
44ae20d3c4
|
generic_platform: prefix subsignals
|
2013-02-20 18:27:04 +01:00 |
|
Sebastien Bourdeauducq
|
38c3566717
|
generic_platform: add name
|
2013-02-14 20:02:35 +01:00 |
|
Sebastien Bourdeauducq
|
ed4d65f2be
|
generic_platform: fix IO signal set when using existing record objects
|
2013-02-13 23:29:33 +01:00 |
|
Sebastien Bourdeauducq
|
feec035cc8
|
generic_platform: get absolute path for added sources
|
2013-02-12 19:16:00 +01:00 |
|
Sebastien Bourdeauducq
|
709845e618
|
generic_platform: fix request
|
2013-02-11 17:54:01 +01:00 |
|
Sebastien Bourdeauducq
|
f13ad035e1
|
Support for command line arguments
|
2013-02-08 22:23:58 +01:00 |
|
Sebastien Bourdeauducq
|
7b8e8a19f3
|
Support adding Verilog/VHDL files
|
2013-02-08 20:25:20 +01:00 |
|
Sebastien Bourdeauducq
|
32dcfc6d02
|
generic_platform: support name remapping
|
2013-02-08 18:27:46 +01:00 |
|
Sebastien Bourdeauducq
|
fef9d0fc78
|
generic_platform: fix typo
|
2013-02-08 17:43:04 +01:00 |
|
Sebastien Bourdeauducq
|
fb5130fc1f
|
Initial version
|
2013-02-07 22:07:30 +01:00 |