6a0a896e96
improve documentation output
2020-11-15 17:07:33 +08:00
6deb750d6e
Improve soc.svd output for eventmanager events
...
Right now no data is created for which bit means what in
the soc.svd file. Attempt to extend event manager finalization
to use "fields" instead of bit positions, so that the SVD
file can auto-generate the events correctly.
2020-11-15 16:33:14 +08:00
05f83ca978
tools/litex_term: minor cleanups (cosmetic).
2020-11-13 11:12:35 +01:00
5097b7ae5c
boards: keep up to date with litex-boards, remove pcie_screamer target.
2020-11-12 18:16:56 +01:00
103c7e90a5
integration/soc/LiteXSoC: add initial add_pcie integration method.
2020-11-12 16:07:40 +01:00
7a4b26d2ba
tools/litex_json2dts: fix missing {.
2020-11-12 14:45:46 +01:00
9c0f687922
build/generic_platform: use script filename as name when no Platform file.
2020-11-11 09:45:21 +01:00
275932f56c
gen/fhdl/verilog: improve clock domain error reporting.
2020-11-10 13:27:29 +01:00
2741fc2ba5
build/generic_programmer: add call method that raises OSError when failing and use it on specific programmers.
...
This will avoid programming errors to be silently ignored and will raise the following error:
OSError: Error occured during OpenOCD's call, please check:
- OpenOCD installation.
- access permissions.
- hardware and cable.
2020-11-10 10:22:57 +01:00
a5bdfe3f4c
software/i2c: add i2c_scan command.
2020-11-10 09:47:28 +01:00
ce9f24748f
soc/cores/bitbang/I2C: use Tristate on SDL/SDA and only drive low (rely on I2C Pull-Ups for high).
2020-11-10 09:46:43 +01:00
221ea4c31a
tools/remote/comm_udp: revert try/except (was probably needed with CommUDP's max_length = 4).
2020-11-09 16:36:04 +01:00
5aa70d975c
tools/litex_server: revert CommUDP's max length to 1 (needs more testing).
2020-11-09 16:35:04 +01:00
1d04b1dd83
software/liblitesdcard: Operate the SDCard in 3.3V/High Speed.
...
SDR50/Driver strength configuration is for 1.8V that is no longer supported
(for simplicity).
2020-11-09 15:39:54 +01:00
b3a42d76ce
cores/cpu/microwatt: fix non irq variant, add standard+irq/"standard+gdhl+irq variants, move XICSSlave after CPU class.
2020-11-09 13:31:11 +01:00
3673f38d63
Merge pull request #653 from gsomlo/gls-dt-cpufreq
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RFC: json2dts: set CPU clock-frequency and SoC bus-frequency
2020-11-09 12:40:15 +01:00
ecaf69fe78
Merge pull request #688 from rprinz08/master
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Fix check for wrong named attributes
2020-11-09 11:22:08 +01:00
0627c01d89
soc/cores/spi_opi: move add_timing_constraints after __init__ to ease readability (first describe the logic then add the constraints).
2020-11-09 11:15:00 +01:00
5587ee5eea
Merge pull request #690 from betrusted-io/master
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Add arbitrary command (eg. write) capability to SPI DOPI
2020-11-09 11:12:13 +01:00
80883ef37e
Merge pull request #689 from DurandA/patch-7
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libcompiler_rt: Remove duplicate mulsi3.o in Makefile
2020-11-09 11:08:29 +01:00
50a47f551e
soc/cores: create ram directory and move SPRAM/LRAM implementation to it.
...
Will ease maintenance and future additions similarly to clock wrappers. Provide
retro-compatibily layer for Up5kSPRAM that we could remove after next release.
2020-11-09 11:04:31 +01:00
ea8be6adcd
targets/kcu105: add missing AsyncResetSynchronizer import.
2020-11-09 10:40:36 +01:00
cecb36d608
test/test_clock: update with new supported devices.
2020-11-09 10:37:20 +01:00
14e196ab5d
soc/cores/clock: create directory and split code in separate files to ease maintenance/adding new devices.
...
clock.py was originally created/prototyped for 7-Series FPGAs, but has since been extended to almost all
FPGA devices supported by LiteX making it large enough to justify the split.
soc/cores/clock/__init__.py provides the retro-compatibily layer.
2020-11-09 10:33:12 +01:00
036ea48a4d
update constraints to be in-line with litex methodology
2020-11-09 16:43:01 +08:00
383ea3e252
Merge pull request #692 from davidcorrigan714/master
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Lattice NX PLL Support
2020-11-09 09:33:01 +01:00
a6fd7b5d37
Lattice NX PLL Support
2020-11-08 20:34:10 -06:00
b59711f89f
Merge remote-tracking branch 'origin/master'
2020-11-08 14:35:41 +08:00
2c36098f45
libcompiler_rt: Remove duplicate mulsi3.o in Makefile
2020-11-08 03:21:39 +01:00
09ecd9abc9
Make commUDP more reliable in case of bad Ethernet connection
2020-11-07 11:32:50 +01:00
1c039389f2
Fix check for wrong named attributes
2020-11-07 11:13:51 +01:00
d892c6f8f5
minor bug fixes in spi writing; USB-based flashing is not working
2020-11-07 03:57:46 +08:00
9359aa0688
tools/litex_server: revert CommUDP's max length to 4 now that https://github.com/enjoy-digital/liteeth/issues/52 is fixed).
2020-11-06 19:50:25 +01:00
9fe3a42072
software/liblitedra/sdram: minor cleanup, use identical delay after each delay increment.
2020-11-06 16:11:25 +01:00
d1ef64f9fd
tools/litex_server: revert CommUDP's max_length to 1.
...
https://github.com/enjoy-digital/liteeth/issues/52 needs to be investigated before enabling _read_merger
on UDP.
2020-11-06 13:01:56 +01:00
996be95725
tools/litex_sim: also add CPU's dbus to analyzer_signals (to demonstrate triggers in wiki).
2020-11-06 12:49:43 +01:00
fc59bcd833
add facility for burst writing and fix pp4b command bug
2020-11-06 04:43:23 +08:00
61c009a393
revert get_data_mod change (Vexrisv SMP repo has been renamed to pythondata-cpu-vexriscv_smp).
2020-11-05 19:55:18 +01:00
c088cd5d22
cores/clock: only use locked on AsyncResetSynchronizer (already falling on reset) and add delay to reset to prevent interlocks with BIOS reboot command on Xilinx devices.
2020-11-05 19:43:11 +01:00
3e47a6e48b
get_data_mod: fix error message when module not found (pythondata modules are named only with "-" and not "_").
2020-11-05 15:58:32 +01:00
65f19b5c4a
integration/soc/add_sdram: add with_bist parameter to add LiteDRAM's BIST.
...
sdram_bist command will then be available in the BIOS:
litex> sdram_bist
sdram_bist <burst_length> <random>
litex> sdram_bist 256 0
Starting SDRAM BIST with burst_length=256 and random=0
WR-SPEED(MiB/s) RD-SPEED(MiB/s) TESTED(MiB) ERRORS
473 455 0 0
473 455 25 0
473 455 50 0
473 455 75 0
473 455 100 0
473 455 125 0
473 455 150 0
473 455 175 0
473 455 200 0
473 455 225 0
WR-SPEED(MiB/s) RD-SPEED(MiB/s) TESTED(MiB) ERRORS
473 455 250 0
473 455 275 0
473 455 300 0
473 455 325 0
473 455 350 0
473 455 375 0
473 455 400 0
473 455 425 0
473 455 450 0
473 455 475 0
WR-SPEED(MiB/s) RD-SPEED(MiB/s) TESTED(MiB) ERRORS
473 455 500 0
473 455 525 0
473 455 550 0
473 455 575 0
473 455 600 0
473 455 625 0
litex>
2020-11-05 13:41:37 +01:00
97b35a0771
software/liblitedram/bist: update generator/checker control to configure end CSR.
2020-11-05 13:39:48 +01:00
3dffdbf628
build/xilinx: add missing \n on error reporting.
2020-11-04 11:32:25 +01:00
897b2ea412
boards/targets: add rst signal to CRG to allow full reset of the SoC on reboot command.
2020-11-04 11:15:04 +01:00
ffc554dede
soc/integration/core: Connect SoCController's reset to CRG.rs do full reset of the SoC with reboot when signals are presents.
2020-11-04 10:58:16 +01:00
2c504783ca
bios/cmd/cmd_bios: add leds command to set leds value.
...
Can be used as a first/simple/visual example to start interacting with the hardware from the CPU/BIOS.
2020-11-04 10:22:14 +01:00
db836e8e5d
build: add toolchain check before running build script and improve error reporting.
2020-11-04 09:42:18 +01:00
6e806ce60c
refactor SPI DOPI interface to support arbitrary commands, not jsut reads
...
lays the groundwork for doing page programming and sector erasing
2020-11-04 04:39:47 +08:00
f8cadc7b04
software/liblitesata/init: avoid reset when SATA PHY already ready (gateware is already hotplug capable).
2020-11-03 19:20:43 +01:00
b8d48385f6
Merge pull request #684 from sergachev/master
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cores/cpu/zynq7000: fix axi hp slave registration
2020-11-03 14:53:10 +01:00
bunnie
Florent Kermarrec
davidcorrigan714
Arnaud Durand
rprinz08