c8fcaaea2d
integration/soc: use self.irq.enabled instead of hasattr(self.cpu, "interrupt").
2020-11-30 10:17:03 +01:00
146068b048
integration/soc/SoCIRQHandler: be sure IRQs can only be added when enabled.
...
This prevents adding peripherals that requires IRQ support to SoC not supporting
them. Enabling is done automatically when a CPU with interrupt support is added,
but this can also be added manually.
2020-11-30 10:06:45 +01:00
b02753ecfa
tools/comm_udp/litex_server: add --udp-scan args to scan network for available Etherbone/UDP devices.
...
litex_server --udp --udp-scan --udp-ip=192.168.1.x --udp-port=1234
Etherbone scan on 192.168.1.x network:
- 192.168.1.20
- 192.168.1.50
2020-11-26 13:33:20 +01:00
c3660379db
tools/remote/comm_udp: probe Etherbone server on open().
2020-11-26 09:06:52 +01:00
ad62e15d98
tools/litex_server: move PCIe specific bar renaming/enable to comm_pcie.
2020-11-25 16:25:31 +01:00
595c6738a3
tools/remote/etherbone: speed up encoding/decoding.
2020-11-25 16:08:12 +01:00
3d2574a488
tools/remote/comms: base CommXY on CSRBuilder to allow using Comms directly in python scripts.
...
This way, user scripts can be use RemoteClient (communicating with the Server that has
already been opened on the right interface) or directly use CommXY in the scripts.
Using RemoteClient is more generic but can be slower (due to the Etherbone encoding between
the client and server). On fixed configuration using CommXY directly can then be faster
and also avoid manual opening of the server.
2020-11-25 15:05:28 +01:00
2c3687983c
tools/litex_server/client: cleanup.
2020-11-25 11:34:12 +01:00
fa9149720f
tools/remote/comm_udp: keep up to date with new encoding/decoding.
2020-11-25 11:33:44 +01:00
c003293b31
tools/remote/etherbone: simplify/speed up decoding.
2020-11-25 11:33:02 +01:00
01e75addff
tools/remove/etherbone: simplify/speed up encoding.
2020-11-25 10:00:28 +01:00
2a1df9beeb
tools/remote/etherbone: replace merge_bytes with direct call to int.from_bytes.
2020-11-25 09:11:33 +01:00
4d5dca2d74
tools/remote/etherbone: replace split_bytes by direct call to int.to_bytes.
2020-11-25 09:07:58 +01:00
9b696373a2
tools/remove/etherbone: cosmetic cleanup, add assert for maximum burst size (255).
2020-11-25 08:53:11 +01:00
f918d0bf02
tools/remove: add 0x to hex debug prints.
2020-11-24 14:06:46 +01:00
05f83ca978
tools/litex_term: minor cleanups (cosmetic).
2020-11-13 11:12:35 +01:00
7a4b26d2ba
tools/litex_json2dts: fix missing {.
2020-11-12 14:45:46 +01:00
221ea4c31a
tools/remote/comm_udp: revert try/except (was probably needed with CommUDP's max_length = 4).
2020-11-09 16:36:04 +01:00
5aa70d975c
tools/litex_server: revert CommUDP's max length to 1 (needs more testing).
2020-11-09 16:35:04 +01:00
3673f38d63
Merge pull request #653 from gsomlo/gls-dt-cpufreq
...
RFC: json2dts: set CPU clock-frequency and SoC bus-frequency
2020-11-09 12:40:15 +01:00
09ecd9abc9
Make commUDP more reliable in case of bad Ethernet connection
2020-11-07 11:32:50 +01:00
1c039389f2
Fix check for wrong named attributes
2020-11-07 11:13:51 +01:00
9359aa0688
tools/litex_server: revert CommUDP's max length to 4 now that https://github.com/enjoy-digital/liteeth/issues/52 is fixed).
2020-11-06 19:50:25 +01:00
d1ef64f9fd
tools/litex_server: revert CommUDP's max_length to 1.
...
https://github.com/enjoy-digital/liteeth/issues/52 needs to be investigated before enabling _read_merger
on UDP.
2020-11-06 13:01:56 +01:00
996be95725
tools/litex_sim: also add CPU's dbus to analyzer_signals (to demonstrate triggers in wiki).
2020-11-06 12:49:43 +01:00
0dec446434
tools/litex_client: add utils to dump FPGA identifier and registers and expose it as litex_cli.
...
Dump FPGA identifier: litex_cli --ident
Dump FPGA registers: litex_cli --regs
2020-10-22 17:45:45 +02:00
f0abc185e1
targets/sim: update sdram (manual cmd_latency no longer needed).
2020-10-12 18:47:09 +02:00
c77da3a8bc
RFC: json2dts: set CPU clock-frequency and SoC bus-frequency
...
FIXME: timebase-frequency isn't to be used as the raw CPU clock, so
on vexriscv we might want to re-evaluate also setting *that* to the
`CONFIG_CLOCK_FREQUENCY`. Decide whether to keep the SoC's
`bus-frequency` cell, or whether to go with the CPU's `clock-frequency`
only.
2020-10-01 06:59:45 -04:00
ba2ff8cf71
tools/litex_sim: update get_sdram_phy_settings (rd/wrcmdphase no longer exposed as PhySettings).
2020-10-01 11:27:33 +02:00
2b62802961
tools/litex_sim: minor review cleanup.
2020-10-01 10:36:37 +02:00
23e319732c
tools/litex_server: minor review cleanup.
2020-10-01 10:35:11 +02:00
e8c0360fa5
tools/{litex_sim, litex_server}.py: Minor clean-up ( #657 )
...
Enable litex_server debug and create function to add for litex_sim args.
2020-10-01 10:32:44 +02:00
e4555df095
tools/litex_server/pcie: enable pcie device if not already enabledd.
...
Avoid having to do it manually or through a driver.
2020-09-29 13:38:19 +02:00
bc5873f78c
tools/litex_server/pcie: allow passing pcie bar as reported by lspci.
...
ex:
$lspci
[...]
06:00.0 RF controller: Xilinx Corporation Device 7022 (rev 01)
sudo litex_server --pcie --pcie-bar=06:00.0
2020-09-29 13:10:05 +02:00
6d07f01f5b
tools/litex_client/RemoteClient: allow use without local csr.csv file.
...
In some case, we just want to access MMAP manually without having the csr.csv file:
wb = RemoteClient()
wb.open()
wb.read(0x40000000)
wb.close()
2020-09-29 13:01:44 +02:00
7c3fbf1d06
sim: improve tracing reset value and behaviour with sim_debug=False
2020-09-07 15:29:02 +02:00
3fd567c4c9
sim: additional simulation tracing and debugging tools
2020-09-07 15:28:26 +02:00
31afe55821
tools/litex_sim: avoid build/run duplication.
2020-09-03 09:21:37 +02:00
222e3f4003
tools/remote/comm_uart: fix offset on write bursts.
2020-09-02 17:23:56 +02:00
b44ca6d61a
soc/core/uart: add fixed burst support to UARTBone.
...
Allows speeding-up consecutives accesses on the same address. This is currently
used by LiteDRAM bench to speed-up the logging of the BIOS over the crossover UART,
but could be useful for other purposes.
2020-08-28 03:49:50 +02:00
4dab1eb0c8
litex_json2dts: Add support for mor1kx
2020-08-24 08:02:16 +02:00
b8371ef480
tools: add SPDX License identifier to header and specify file is part of LiteX.
2020-08-23 15:37:16 +02:00
abc49964ea
tools/litex_json2dts: add missing copyrights.
2020-08-04 16:38:02 +02:00
aed0dcee4c
setup: add litex_json2dts to console_scripts.
2020-08-04 16:07:53 +02:00
b64209b38b
Merge pull request #620 from antmicro/add_litex_json2dts
...
Add Linux DT generation script
2020-08-04 16:04:57 +02:00
382c1a3a44
Merge pull request #619 from antmicro/jboc/sim-clocker
...
Allow to define multiple simulation clocks
2020-08-04 15:38:28 +02:00
fafa844aa7
json2dts: Add Linux DT generation script
2020-08-04 15:13:17 +02:00
2a3e39b10e
tools/litex_server: enable read_merger with CommUDP.
...
Limited to 4 (current size of the buffer in liteeth.frontend.etherbone).
2020-08-04 10:55:51 +02:00
c1ae7e596c
build/sim: allow for arbitrary clocks generation using clockers
2020-08-03 17:06:38 +02:00
38054874ac
build/sim: use a real timebase in the simulation
2020-08-03 15:21:24 +02:00
Florent Kermarrec
rprinz08
Gabriel Somlo
Vamsi Vytla
Jędrzej Boczar
Mateusz Holenko