Florent Kermarrec
|
cab5b7b8f8
|
link: simplify BFM
|
2014-12-03 09:17:51 +01:00 |
|
Florent Kermarrec
|
6cc8686402
|
link: manage hold
|
2014-12-03 02:06:43 +01:00 |
|
Florent Kermarrec
|
ed97f378ff
|
link: add CRC check to BFM
|
2014-12-02 20:02:43 +01:00 |
|
Florent Kermarrec
|
f2757ef8dd
|
link: fix link_tb (due to others modifications)
|
2014-12-02 19:53:13 +01:00 |
|
Florent Kermarrec
|
31b9132dd9
|
link: improve and clean up crc_tb, scrambler_tb
|
2014-12-02 19:24:46 +01:00 |
Sebastien Bourdeauducq
|
aac34f011f
|
gensoc: support user-defined CSR regions
|
2014-11-30 22:29:26 +08:00 |
|
Sebastien Bourdeauducq
|
8ae3a00a94
|
gensoc: simplify WB address decoding
|
2014-11-30 22:05:51 +08:00 |
|
Sebastien Bourdeauducq
|
4189440eef
|
minicon: small simplifications
|
2014-11-28 08:28:39 +08:00 |
Yann Sionneau
|
edb1622668
|
spiflash: BB write support
|
2014-11-27 23:10:39 +08:00 |
|
Sebastien Bourdeauducq
|
bab6bb7c4a
|
gensoc: fix align
|
2014-11-27 23:05:36 +08:00 |
|
Sebastien Bourdeauducq
|
2cd80990e4
|
minicon: fix use of phy phases
|
2014-11-27 22:13:17 +08:00 |
|
Sebastien Bourdeauducq
|
8418ccafdc
|
minicon: remove unused signals and fix indent
|
2014-11-27 22:12:05 +08:00 |
|
Yann Sionneau
|
cf92821fcf
|
Refactor directory hierarchy of sdram phys and controllers
|
2014-11-27 22:09:10 +08:00 |
|
Yann Sionneau
|
f33b285af1
|
Minicon: small SDRAM controller
|
2014-11-27 22:09:03 +08:00 |
|
Florent Kermarrec
|
5202f89db1
|
ethmac/last_be: remove fake signal (fixed in Migen)
|
2014-11-21 14:48:17 -08:00 |
|
Sebastien Bourdeauducq
|
b7028848b2
|
ethmac: use new EndpointDescription API
|
2014-11-20 22:32:32 -08:00 |
|
Sebastien Bourdeauducq
|
33530e0921
|
ethmac: style/renaming
|
2014-11-20 18:01:48 -08:00 |
|
Sebastien Bourdeauducq
|
7eaa5f7372
|
targets/kc705: avoid ddrphy/ethphy address conflict
|
2014-11-20 17:11:57 -08:00 |
|
Florent Kermarec
|
603c2641bb
|
new Ethernet MAC
|
2014-11-20 16:47:22 -08:00 |
|
Florent Kermarrec
|
2b7779d3b6
|
link: wip bfm
|
2014-11-12 18:20:34 +01:00 |
|
Florent Kermarrec
|
b423c1df4b
|
link: prepare simulation
|
2014-11-11 18:47:34 +01:00 |
|
Florent Kermarrec
|
64ed34b35a
|
clean up
|
2014-11-11 16:15:28 +01:00 |
|
Florent Kermarrec
|
705819f885
|
use new EndpointDescription
|
2014-11-11 14:54:54 +01:00 |
|
Florent Kermarrec
|
67aaf09b53
|
link: SATALinkLayer skeleton
|
2014-11-11 12:29:37 +01:00 |
|
Florent Kermarrec
|
294855e292
|
phy: use primitives dict and use only sata.std
|
2014-11-11 10:19:24 +01:00 |
|
Florent Kermarrec
|
30964db4a1
|
phy: send 2 ALIGN primitives every 256 DWORDs
|
2014-11-11 09:57:43 +01:00 |
|
Sebastien Bourdeauducq
|
f4d6ac8393
|
README: remove compiler-rt download instructions
|
2014-11-06 18:02:02 -08:00 |
|
Sebastien Bourdeauducq
|
09773df186
|
software: make compiler-rt a submodule
|
2014-11-06 18:00:28 -08:00 |
|
Florent Kermarrec
|
353e7fc13b
|
link: add SATALinkLayer skeleton (wip)
|
2014-11-04 22:55:31 +01:00 |
|
Florent Kermarrec
|
8f6354f2a3
|
link: improve crc_tb/ preamble_tb and increase length
|
2014-11-04 17:06:03 +01:00 |
|
Florent Kermarrec
|
c810009387
|
link: add Scrambler and testbench
|
2014-11-04 16:40:21 +01:00 |
|
Florent Kermarrec
|
8062298668
|
link: add CRC and testbench
|
2014-11-04 10:33:11 +01:00 |
|
Florent Kermarrec
|
449daedab7
|
sata/link: add crc and scrambler C models from SATA specification
|
2014-11-03 18:11:14 +01:00 |
|
Florent Kermarrec
|
47b5ff5e33
|
move code and create a directory for each layer
|
2014-11-03 17:38:12 +01:00 |
|
Florent Kermarrec
|
8c5c32751e
|
add input pipe stage option
|
2014-10-28 20:53:26 +01:00 |
|
Florent Kermarrec
|
25e0ccae9a
|
remove DRP ports (won't be used for now)
|
2014-10-28 11:33:15 +01:00 |
|
Florent Kermarrec
|
3f7406a937
|
various fixes and simplifications, SATA1 & SATA2 OK
|
2014-10-28 02:15:19 +01:00 |
|
Florent Kermarrec
|
e2cbb3a048
|
platforms: merge but keep support for iMPACT for now (xc3sprog need to be tested on Windows)
|
2014-10-24 12:32:08 +02:00 |
|
Florent Kermarrec
|
8e4b89849c
|
use new direct access on endpoints
|
2014-10-20 23:13:37 +08:00 |
|
Florent Kermarrec
|
34ed315a48
|
remove trailing whitespaces
|
2014-10-17 17:14:40 +08:00 |
|
Florent Kermarrec
|
d860813dec
|
use new direct access on endpoints
|
2014-10-16 17:57:30 +02:00 |
|
Florent Kermarrec
|
bbfce2b707
|
ctrl: drive txcomwake and not gtx.txcomwake in K7SATAPHYDeviceCtrl
|
2014-10-16 10:38:26 +02:00 |
|
Florent Kermarrec
|
9649b1497c
|
uart2wishbone: fix missing payload.d
|
2014-10-16 09:37:43 +02:00 |
|
Florent Kermarrec
|
2319ee0ab7
|
uart2wishbone: always use payload.d and not .d
|
2014-10-15 12:13:22 +02:00 |
|
Florent Kermarrec
|
027ddc65ca
|
fill __init__.py to simplify imports
|
2014-10-10 17:24:36 +02:00 |
|
Florent Kermarrec
|
bf95ea6c1c
|
mila: simplify usage
|
2014-10-10 16:17:12 +02:00 |
|
Florent Kermarrec
|
d0c9838dca
|
uart2wishbone: share UARTRX and UARTTX with MiSoC
|
2014-10-10 15:15:58 +02:00 |
|
Sebastien Bourdeauducq
|
20528c622a
|
mor1kx: sync
|
2014-10-10 15:38:05 +08:00 |
|
Sebastien Bourdeauducq
|
e53fb88b85
|
uart: minor cleanup and fix
|
2014-10-10 15:33:27 +08:00 |
|
Florent Kermarrec
|
5e5f436aa6
|
uart: split it and use dataflow
This make the code easier to understand and allow the reuse of UARTRX & UARTTX
on designs without CPU (e.g miscope).
|
2014-10-10 15:24:47 +08:00 |