Dolu1990
943d652362
cores/naxriscv match axi width
2023-09-05 18:13:27 +02:00
Gwenhael Goavec-Merou
99cb46fd3e
build/efinix/ifacewriter: fix CLKOUTx_PHASE configuration for recent efinity, keep backward compatibility
2023-09-05 16:44:47 +02:00
Icenowy Zheng
7afe06a60c
clock/gowin_gw5a: change allowed frequency range for GW5A- prefix
...
When targeting GW5A-25 ES, the Gowin IDE has a more strict frequency
range.
Change the range when GW5A- is matched to this.
Signed-off-by: Icenowy Zheng <uwu@icenowy.me>
2023-09-05 16:50:49 +08:00
Josuah Demangeon
5e4628f1fe
build/lattice/radiant: fix uname() not prefixed by 'os.'
2023-09-04 19:30:29 +02:00
enjoy-digital
6c6cfeae7f
Merge pull request #1763 from josuah/radiant_wsl2
...
Allow use of Windows-side (.exe) Radiant toolchain
2023-09-03 19:27:32 +02:00
Josuah Demangeon
2e6ddd9dd9
build/lattice/radiant: allow use of Windows-side (.exe) radiant toolchain under WSL2
2023-09-02 22:28:40 +02:00
Dolu1990
8853215033
Merge pull request #1762 from motec-research/dma_fix
...
proof of concept coherent dma fix
2023-09-02 08:22:40 +02:00
Andrew Dennison
1bb4d299a6
vexrisc_smp: fix DMA bus address_width calculation
2023-09-02 11:46:11 +10:00
Andrew Dennison
48ab96fd43
soc/intregation: fix cpu name in logging
...
Fixed CPU name being reported as irq name in logging.
```
INFO:SoC:CPU vexriscv_smp adding Interrupt(s).
INFO:SoCIRQHandler:noirq IRQ added at Location 0.
INFO:SoC:CPU noirq adding DMA Bus.
INFO:SoCDMABusHandler:Creating Bus Handler...
```
2023-09-02 11:46:11 +10:00
Florent Kermarrec
57faa9102f
CHANGES: Update.
2023-09-01 12:40:03 +02:00
Florent Kermarrec
f473261bc6
soc/dma_bus: Make SoCDMABusHandler use the Bus Standard of the DMA Bus defined in the CPU.
...
Also simplify code by using automatic Bus conversion of SoCBusHandler.
2023-09-01 12:19:11 +02:00
Florent Kermarrec
db2ad78860
interconnect/wishbone: Add address_width property to make sure all interfaces (Wishbone/AXI-Lite/AXI) have it.
2023-09-01 12:16:15 +02:00
enjoy-digital
33efa09663
Merge pull request #1760 from motec-research/dts_linux_fix
...
tools/litex_json2dts_linux: fix missed sdcard_ references
2023-09-01 10:46:04 +02:00
Richard Tucker
058cdd646b
tools/litex_json2dts_linux: fix missed sdcard_ references
2023-09-01 16:54:41 +10:00
enjoy-digital
14012263af
Merge pull request #1758 from motec-research/spi_mmap_fix
...
soc/cores/spi_mmap: Fix clock divider
2023-09-01 08:38:53 +02:00
Radek Pesina
d494e30166
soc/cores/spi_mmap: Fix clock divider
2023-09-01 12:34:51 +10:00
Florent Kermarrec
405296b7fd
interconnect/axi/axi_full: Fix missing switch to LiteXModule.
2023-08-31 19:36:21 +02:00
Gwenhael Goavec-Merou
516038ce76
soc/cores/clock/efinix: don't hardcore create_clock (fix warning because clock is created after set_false_path), explicit clock name (fix warning when signal is absorbed)
2023-08-31 17:24:58 +02:00
Gwenhael Goavec-Merou
fadf47d353
build/lattice/trellis: fix add_period_constraint signature (missing keep arg)
2023-08-31 16:52:48 +02:00
Florent Kermarrec
41357aba7d
xilinx/vivado: Fix issue with #1755 .
2023-08-31 16:38:50 +02:00
Florent Kermarrec
ad924a522a
interconnect/stream/AsyncFIFO: Remove Efinix workaround since seems to be solved with Efinity 2023.x.
2023-08-31 16:03:52 +02:00
enjoy-digital
124e0d22c9
Merge pull request #1755 from enjoy-digital/allows_clk_name_override
...
build/xx/toolchains: allows override clock naming
2023-08-31 15:57:39 +02:00
Gwenhael Goavec-Merou
46800176ae
build/xx/toolchains: allows override clock naming
2023-08-31 15:18:15 +02:00
Gwenhael Goavec-Merou
2a7caa2696
build: all platforms: override add_period_constraint only when required
2023-08-31 12:29:09 +02:00
Gwenhael Goavec-Merou
3f43481eb9
build/efinix/efinity: build_timing_constraints: set_false_path is unidirectional -> add another one to -> from_
2023-08-31 11:42:07 +02:00
Gwenhael Goavec-Merou
a071cc343d
litex/soc/integration/soc: add_etherxx: when eth_rx_clk is eth_tx_clk only apply constraints on eth_rx_clk
2023-08-31 11:36:24 +02:00
Florent Kermarrec
9854c9f322
CHANGES: Update.
2023-08-30 18:11:11 +02:00
Florent Kermarrec
ff0df100e9
build/efinix: Add get_pin (from sig) to EfinixPlatform and use it to simplify/fix IOs exclusion.
2023-08-30 18:08:40 +02:00
Florent Kermarrec
72590dfde3
software/libliteeth: Fix udp_set_callback warning.
2023-08-30 17:44:00 +02:00
Florent Kermarrec
434e2225ea
software/liblitedram: Fix swap_bit warning.
2023-08-30 17:22:57 +02:00
Florent Kermarrec
c2714df198
build/efinix/common: Add initial EfinixDDROutput/EfinixDDRInput implementation.
...
Still need to figure out a few things:
- Clk is passed as a string for now.
- IOs exclusion still handled externally.
2023-08-30 11:28:48 +02:00
Florent Kermarrec
c0ab4ed1c1
build/io: Allow passing clk as str on DDRInput/Output, wrap DDROutput IOs and minor ident fixes.
2023-08-30 10:52:13 +02:00
Florent Kermarrec
6dff371835
build/efinix/common: Simplify IO exclusion in EfinixTristateImpl and fix corner cases (ex eth_mdio that was not automatically excluded).
2023-08-30 09:16:46 +02:00
Florent Kermarrec
9528f89d45
CHANGES: Update.
2023-08-29 17:15:45 +02:00
Florent Kermarrec
85dadb827a
clock/gowin_gw5a: Fix copyright.
2023-08-29 14:25:04 +02:00
enjoy-digital
c122fef5ac
Merge pull request #1741 from Icenowy/gw5apll
...
soc/cores/clock: initial GW5A support
2023-08-29 14:21:02 +02:00
Icenowy Zheng
1636c0ef8d
soc/cores/clock: initial GW5A support
...
GW5A has different PLLs than GW1N/GW2A, with multiple individual
ODIV's. GW5A-25 has a different PLL with GW5A[S]T-138, with lack of
dynamic control.
Add basic support for them.
Signed-off-by: Icenowy Zheng <uwu@icenowy.me>
2023-08-29 15:39:25 +08:00
Dolu1990
a4498dcd03
nax dma wip, WARNING soc.py
2023-08-28 18:57:45 +02:00
Florent Kermarrec
82602f660c
interconnect/stream: Fix #1736 .
2023-08-28 16:19:31 +02:00
Florent Kermarrec
70e52b76fa
CHANGES: Update.
2023-08-28 16:04:43 +02:00
Florent Kermarrec
d29d2c09bb
interconnect/stream: Minor review/cleanup.
2023-08-28 16:02:52 +02:00
enjoy-digital
8efcc4fdea
Merge pull request #1736 from rowanG077/buf-endpoint-cfg
...
soc/interconnect/stream: BufferizeEndpoints params
2023-08-28 15:58:46 +02:00
Gwenhael Goavec-Merou
f7b35f09ae
build/efinix/efinity: don't hardcode efinity version, read from scripts/sw_version.txt
2023-08-28 14:43:17 +02:00
Florent Kermarrec
8f54386aab
gen/fhdl/module: Add some comments.
2023-08-24 09:17:35 +02:00
enjoy-digital
a125f9aa6f
Merge pull request #1752 from enjoy-digital/naxriscv_update
...
cpu/naxriscv: Update recommended version.
2023-08-22 16:29:08 +02:00
Florent Kermarrec
6d8c04b401
cpu/naxriscv: Update recommended version.
2023-08-22 15:50:08 +02:00
Dolu1990
8f7f97a713
fix plic/clint regions + dts
2023-08-18 19:29:41 +02:00
Dolu1990
8302cf2e79
got nax 2 cores to run linux
2023-08-18 10:01:28 +02:00
Gwenhael Goavec-Merou
1520d0f382
Merge pull request #1745 from alexey-morozov/master
...
Litex offline installation fix
2023-08-16 15:18:57 +02:00
Alexey Morozov
cd1012470e
To allow offline installation, the "liteiclink" package has to be installed before the "liteeth" package. Otherwise, to satisfy the dependency requirements, the setup will attempt to download the "liteiclink" package from the internet and will consequently fail.
2023-08-16 09:39:03 +02:00
