Sebastien Bourdeauducq
|
a7b4550e59
|
sdramphy/initsequence: cleanup and expose DDR3 MR1 value
|
2014-09-03 14:21:30 +08:00 |
Florent Kermarrec
|
114890ee80
|
sdramphy/initsequence: clean up mr1/mr2 computation on DDR3 and enable Dynamic ODT
|
2014-09-02 10:54:29 +08:00 |
|
Sebastien Bourdeauducq
|
2234f50223
|
k7ddrphy: add bitslip control for incoming DQ
|
2014-09-01 19:54:39 +08:00 |
|
Sebastien Bourdeauducq
|
0eeb0ad9eb
|
targets/kc705: add ddrphy to CSR map
|
2014-09-01 16:40:10 +08:00 |
|
Sebastien Bourdeauducq
|
6decb357f1
|
bios: add sdrrderr
|
2014-09-01 15:23:37 +08:00 |
|
Sebastien Bourdeauducq
|
57335bdf3f
|
bios: add DQ filtering to sdrrd, add sdrrdbuf command
|
2014-09-01 14:58:58 +08:00 |
|
Sebastien Bourdeauducq
|
5483b37c8f
|
k7ddrphy: write leveling and read calibration support
|
2014-08-31 21:54:28 +08:00 |
|
Sebastien Bourdeauducq
|
19abe2b888
|
k7ddrphy: do not register T at SERDES (fixes timing problem)
|
2014-08-31 21:53:35 +08:00 |
|
Sebastien Bourdeauducq
|
a2096ff083
|
libcompiler-rt: add moddi3
|
2014-08-28 16:54:12 +08:00 |
|
Sebastien Bourdeauducq
|
541e5abbc7
|
k7ddrphy: update comment
|
2014-08-22 19:02:57 +08:00 |
|
Sebastien Bourdeauducq
|
66fe45ba96
|
k7ddrphy: decrease CAS latency to account for cmd/data flight time
|
2014-08-22 18:46:01 +08:00 |
|
Sebastien Bourdeauducq
|
b94647ab16
|
k7ddrphy: suppress idiotic bitgen warning about ISERDES IOBDELAY parameter
|
2014-08-22 18:45:25 +08:00 |
|
Sebastien Bourdeauducq
|
35327a427f
|
targets/kc705: BIOS XIP
|
2014-08-22 17:13:10 +08:00 |
|
Sebastien Bourdeauducq
|
6b35c7b8ea
|
targets/ppro: reduce SPI flash clock frequency
|
2014-08-22 15:24:14 +08:00 |
|
Sebastien Bourdeauducq
|
7b10f1821f
|
targets/ppro: fix BIOS address
|
2014-08-22 15:24:00 +08:00 |
|
Florent Kermarrec
|
3eabec28cd
|
make.py: add set_flash_proxy_dir to flash-bios
|
2014-08-22 15:04:50 +08:00 |
|
Sebastien Bourdeauducq
|
2f2a57dd34
|
targets/ppro: clean up indentation
|
2014-08-22 14:41:28 +08:00 |
|
Florent Kermarrec
|
1c381acc6f
|
k7ddrphy: fix read_latency (CL is 2 sys_clk since we use quarter rate)
|
2014-08-14 22:46:06 +08:00 |
|
Florent Kermarrec
|
acbba37f5f
|
k7ddrphy: set bitslip to 0 on ISERDESE2 (needed at least for sim)
|
2014-08-14 22:46:06 +08:00 |
|
Florent Kermarrec
|
2e4bfe154f
|
k7ddrphy: add ODELAYE2 on dm path to match dq path (ODELAYE2 even configure with a delay of 0 generates a delay)
|
2014-08-14 22:46:06 +08:00 |
|
Florent Kermarrec
|
bb85f29f91
|
k7ddrphy: fix write_latency and take care of OSERDESE2 latency on oe
|
2014-08-14 22:46:06 +08:00 |
|
Florent Kermarrec
|
85b29c883a
|
sdramphy/initsequence: fix and add format_mr0 function
|
2014-08-14 14:17:54 +08:00 |
|
Florent Kermarrec
|
9844c25df9
|
k7ddrphy: add SERDES reset
|
2014-08-14 14:16:41 +08:00 |
|
Florent Kermarrec
|
194a5a0491
|
lasmicon: fix reset_n level
|
2014-08-14 14:15:48 +08:00 |
|
Sebastien Bourdeauducq
|
3a960e9e6a
|
flash_extra: use new programmer
|
2014-08-09 14:39:38 +08:00 |
|
Sebastien Bourdeauducq
|
a6c55d8dde
|
make.py: do not use prog.needs_flash_proxy
|
2014-08-09 14:38:56 +08:00 |
|
Sebastien Bourdeauducq
|
4d2623a87e
|
mor1kx: sync
|
2014-08-09 14:32:57 +08:00 |
|
Sebastien Bourdeauducq
|
c8dd4d2b40
|
k7ddrphy: send rddata_valid on all phases
|
2014-08-09 11:00:13 +08:00 |
|
Sebastien Bourdeauducq
|
41c8c172b5
|
targets/kc705: integrate DDR3
|
2014-08-08 21:58:41 +08:00 |
|
Sebastien Bourdeauducq
|
0ebdf2be6d
|
bios/sdram: cleanup
|
2014-08-08 21:57:58 +08:00 |
|
Sebastien Bourdeauducq
|
b61dced909
|
bios/sdram: set ODT and RESET_N through DFII
|
2014-08-08 21:57:42 +08:00 |
|
Sebastien Bourdeauducq
|
8deadc5760
|
dfii: drive ODT and RESET_N
|
2014-08-08 21:56:35 +08:00 |
|
Sebastien Bourdeauducq
|
1322c0484b
|
lasmicon: drive ODT and RESET_N
|
2014-08-08 21:55:34 +08:00 |
|
Sebastien Bourdeauducq
|
0550cbb3ce
|
lasmicon: add CWL to PHY settings
|
2014-08-08 21:55:12 +08:00 |
|
Sebastien Bourdeauducq
|
777ebb7875
|
sdramphy/gensdrphy: fix rddata_en generation
|
2014-08-08 21:41:07 +08:00 |
|
Sebastien Bourdeauducq
|
a2c7ff4c0c
|
sdramphy: initial K7 DDR3 support
|
2014-08-08 21:28:26 +08:00 |
|
Florent Kermarrec
|
293ac09673
|
sdramphy/bios: make sdrrd/sdrwr generic
|
2014-08-08 19:25:10 +08:00 |
|
Sebastien Bourdeauducq
|
cfc37a3fa5
|
sdramphy/initsequence: rewrite DDR3 initialization sequence
|
2014-08-08 19:15:05 +08:00 |
|
Sebastien Bourdeauducq
|
e8db842538
|
s6ddrphy: fix DFI interface data width computation
|
2014-08-08 19:14:15 +08:00 |
|
Sebastien Bourdeauducq
|
efb2466c7e
|
gensoc: add id for KC705
|
2014-08-06 23:53:51 +08:00 |
|
Sebastien Bourdeauducq
|
fb48b89bac
|
platforms/kc705: generate clocks for SDRAM
|
2014-08-06 23:53:26 +08:00 |
|
Sebastien Bourdeauducq
|
ca6d6954c1
|
targets/ppro: use migen reset synchronizer
|
2014-08-06 19:38:11 +08:00 |
|
Florent Kermarrec
|
d1ff43faa7
|
gensoc/cpuif: do not generate access functions for registers > 64 bits
|
2014-08-04 22:38:19 +08:00 |
|
Sebastien Bourdeauducq
|
37968e649b
|
targets/kc705: use PLL for clocking
|
2014-08-03 21:42:39 +08:00 |
|
Sebastien Bourdeauducq
|
1a09eb7a19
|
mor1kx: sync
|
2014-08-03 15:57:55 +08:00 |
|
Sebastien Bourdeauducq
|
61eae462f3
|
README: update
|
2014-08-03 15:48:55 +08:00 |
|
Sebastien Bourdeauducq
|
f7a7137127
|
targets: add basic KC705
|
2014-08-03 15:48:30 +08:00 |
|
Sebastien Bourdeauducq
|
213cb43ae5
|
Keep only basic SoC designs in MiSoC
|
2014-08-03 12:30:15 +08:00 |
|
Sebastien Bourdeauducq
|
9395214d75
|
remove stale programmer.py
|
2014-08-01 12:34:38 +08:00 |
|
Florent Kermarrec
|
62c9043d07
|
move programmer to mibuild
|
2014-08-01 08:03:53 +08:00 |