Commit Graph

7253 Commits

Author SHA1 Message Date
Florent Kermarrec a99b4cac48 build/efinix: Minor initial cleanups. 2021-10-13 09:42:39 +02:00
enjoy-digital eafa0fe83e
Merge pull request #1066 from fjullien/efinix
Initial Efinix support.
2021-10-13 09:17:32 +02:00
Florent Kermarrec 5e3e78f760 soc/add_pcie: Automatically set Endpoint's endianness to PHY's endianness. 2021-10-12 15:46:35 +02:00
enjoy-digital f93b6b9f27
Merge pull request #1065 from shenki/microwatt-picolibc-family
microwatt: Fix family property
2021-10-12 09:08:57 +02:00
Florent Kermarrec a489dadfbc cpu/CPUNone: Add ethmac to mem_map as temporary build workaround for --cpu-type=None --with-ethernet. 2021-10-12 09:02:48 +02:00
Joel Stanley 79ae6a99ab microwatt: Fix family property
In commit 061b89beff ("cpu/picolibc: Add family property to CPUs and
directly use it for picolibc.") a family was added for meson cross
compilation, but this doesn't exist, leading to the following warning:

 WARNING: Unknown CPU family powerpc, please report this at https://github.com/mesonbuild/meson/issues/new

Instead use ppc64. While this seems wrong for a ppc64le machine, it
appears to be what meson expects.

Signed-off-by: Joel Stanley <joel@jms.id.au>
2021-10-12 17:21:09 +10:30
Florent Kermarrec 96cfb44851 soc: Raise custom SoCError Exception and disable traceback/exception since already described. 2021-10-12 08:35:14 +02:00
enjoy-digital 975ec20d1e
Merge pull request #1061 from osterwood/patch-1
Update icestorm.py with u4k device, since Yosys can target it
2021-10-11 10:21:23 +02:00
Chris Osterwood 665665e1cc
Update icestorm.py with u4k device, since Yosys can target it 2021-10-08 15:20:39 -04:00
Florent Kermarrec db20cb172d cores/video/VideoFrameBuffer: Add missing ClockDomainsRenamer on Converter (thanks @rdolbeau).
Converter was not running in the right clock domain in ((dram_port.data_width > depth) and clock_faster_than_sys) case.
2021-10-08 14:33:04 +02:00
Florent Kermarrec f508b131ea cores/video: Change depth parameter to format (more explicit and we'll maybe want to support other video formats). 2021-10-08 14:28:04 +02:00
enjoy-digital 6d317d0882
Merge pull request #1053 from rdolbeau/fb_rgb565
Add 16-bits, RGB565 FB support in simple-framebuffer
2021-10-08 14:15:10 +02:00
Florent Kermarrec 9f0a03100d litex_setup: Add more comment, fix checkout when sha1 starting with 0. 2021-10-07 19:03:29 +02:00
gsomlo 1629bcbf30
Merge pull request #1058 from gsomlo/gls-rocket-smp-ecp5
cpu/rocket: add dual-core (smp) variants
2021-10-07 09:04:08 -04:00
Gabriel Somlo 18bd8f3770 cpu/rocket: add dual-core (smp) variants
- 2-core "linux" (fpu-less) variants with double, quad mem. bus width
2021-10-06 08:48:27 -04:00
Florent Kermarrec f03a15820b tools/litex_sim: Remove useless pre_run_callback toolchain attribute. 2021-10-06 09:16:08 +02:00
enjoy-digital 04885a5d77
Merge pull request #1057 from antmicro/rocket-asm-alignment
cpu/rocket: naturally align data defined in crt0.S
2021-10-04 17:57:43 +02:00
Florent Kermarrec 99f3498f2d cores/icap/ICAP: Add Register read capability.
Useful to get some internal status, ex the IDCode or know if the executed bistream
in a multiboot configuration is the operational or fallback one.
2021-10-04 17:22:57 +02:00
Jakub Piecuch 771897fa37 cpu/rocket: naturally align data defined in crt0.S
The startup code accesses this data using sd/ld instructions, which
require that the address being accessed is 8-byte aligned.
The .dword asm directive does NOT imply any alignment, so we need
to force it using the .align directive.
2021-10-04 15:22:13 +02:00
Florent Kermarrec 3504904c09 cores/icap/ICAP: Rewrite using with an FSM instead of Timeline (will be easier to extend). 2021-10-04 15:06:03 +02:00
Florent Kermarrec 9416e30249 test/test_icap: Add IPROG sequence check. 2021-10-04 14:41:38 +02:00
Florent Kermarrec cb2f2d7021 cores/icap/ICAP: Rewrite using constants and cleanup. 2021-10-04 14:25:40 +02:00
Florent Kermarrec 1f2b143c66 cores/icap: Add Configuration Registers and Commands definition. 2021-10-04 13:35:36 +02:00
Florent Kermarrec 6b3b243bb3 cores/icap: Fix/Update comment. 2021-10-04 11:37:40 +02:00
Florent Kermarrec cb6861e1c8 build: Add initial/minimal QuickLogic build support. 2021-10-01 11:42:56 +02:00
enjoy-digital 16702c44fe
Merge pull request #1055 from gsomlo/gls-pico-warn-64
64-bit follow-up for picolibc warning fixes
2021-10-01 10:49:07 +02:00
Gabriel Somlo d92f10dfb0 64-bit follow-up for picolibc warning fixes
Providing "uint32_t" to printf's "%ld" results in warnings on 64-bit
builds: use "unsigned long" instead.
2021-09-30 20:26:40 -04:00
Romain Dolbeau bf004d48e9 Add 16-bits, RGB565 FB support in simple-framebuffer 2021-09-30 19:40:03 +02:00
Florent Kermarrec 77283d3d8d software: Fix picolibc compilation warnings. 2021-09-30 19:24:58 +02:00
Florent Kermarrec 841732f38f software/liblitesata: Fix compilation with picolibc. 2021-09-30 18:56:01 +02:00
enjoy-digital 7b7fd25d5d
Merge pull request #1054 from niw/fix_disk_read_arg_name
FIX: arg name is changed.
2021-09-30 17:44:33 +02:00
Yoshimasa Niwa abcf5f1d7b FIX: arg name is changed. 2021-09-30 02:56:19 -07:00
Florent Kermarrec 47e4a1b437 tools/litex_term: Avoid staying in safe mode on next upload when previous calibration failed. 2021-09-30 10:11:48 +02:00
enjoy-digital 4563ccae18
Merge pull request #1052 from developandplay/patch-5
Add ninja to toolchain setup
2021-09-30 09:33:28 +02:00
developandplay 5e2d03dad7
Add ninja to toolchain setup
In addition to meson I had to install ninja for the picolibc update.
Not sure if it was just an issue on my system but wanted to flag it.
2021-09-30 00:10:45 +02:00
Florent Kermarrec 5661480409 tools/litex_term: Add automatic inter-frame delay calibration and --safe mode.
By default, litex_term will now automatically try to find the best inter-frame delay/payload length
parameters to optimize upload speed. The --safe mode can also be used to disable outstanding frames
(and then wait ack for each frame), it will be slow on regular UARTs (that have high round-trip
latencis) but should always work.
2021-09-29 18:41:06 +02:00
Florent Kermarrec 80cb53fb04 software/bios/boot: Allow frame reception to time out during serial boot and do some cleanup/add comments.
Allowing the serial boot to time out during frame reception allows doing test on the Host side to
calibrate the minimum inter-frame delay and maximum payload length.

In the future, we should probably compute the CRC directly during frame reception and do the mempcpy
of frame N during the reception of frame N+1 to avoid these inter-frame constraints.
2021-09-29 18:33:59 +02:00
Franck Jullien 93c470aecb Efinix: add a local video.py with VideoLVDSPHY for testing 2021-09-28 18:08:03 +02:00
Franck Jullien a08c5201ad Efinix: improve ifacewriter + misc 2021-09-28 18:06:57 +02:00
Franck Jullien 45961f733b Efinix: instance of dbparser class now in platform 2021-09-28 18:06:23 +02:00
Franck Jullien b2e09832e5 Efinix: dbparser, add get_gpio_instance_from_pin 2021-09-28 18:04:49 +02:00
Franck Jullien 32f4d246f4 Efinic ConstraintManager improve delete method 2021-09-28 18:04:27 +02:00
Florent Kermarrec 5a35aa9df6 software/libliteeth: Fix missing prototype warnings. 2021-09-28 17:46:23 +02:00
Florent Kermarrec 7bf6db5f9d README: Add meson package install. 2021-09-28 16:27:30 +02:00
Florent Kermarrec 9a931324c2 get_data_mod: Update pip to pip3 to avoid issues on systems with Python2 still installed. 2021-09-28 16:27:13 +02:00
enjoy-digital a5b3ab1bc9
Merge pull request #1051 from antmicro/picolibc-updates
Picolibc updates
2021-09-28 16:01:29 +02:00
Karol Gugala 9f1108c2fc libc: refactor picolibc build deps
Signed-off-by: Karol Gugala <kgugala@antmicro.com>
2021-09-28 15:17:30 +02:00
Karol Gugala b9c4d7ba51 libc: add _impure_ptr definition
Signed-off-by: Karol Gugala <kgugala@antmicro.com>
2021-09-28 15:17:08 +02:00
Karol Gugala 22f50ec7ff libc: add errno include
This solves missing `__errno` symbol linker errors

Signed-off-by: Karol Gugala <kgugala@antmicro.com>
2021-09-28 15:16:34 +02:00
Florent Kermarrec a588c3b830 software/libc: Disable Atomics support on fgetc/ungetc since seems broken (at least on Rocket). 2021-09-28 14:51:02 +02:00