62c9043d07
move programmer to mibuild
2014-08-01 08:03:53 +08:00
82068267db
mibuild: move programmer to mibuild and create programmer directly in platforms
2014-08-01 08:03:36 +08:00
25b3aff6f1
sdramphy: add init sequence for DDR3
2014-07-31 10:29:32 +08:00
32171da46d
Better UART baudrate generator, and testbench
...
This enables high speed (tested to 4Mbps) operation.
2014-07-31 10:24:52 +08:00
244ee52381
kc705/ddram: use lighter pin syntax
2014-07-30 10:31:26 +08:00
9cf204598a
mibuild/xilinx_vivado: allow sharing Misc constraints with ISE: example: ISE: DIFF_TERM=True VIVADO: set property DIFF_TERM TRUE
2014-07-30 10:10:41 +08:00
2cb7d73870
mor1kx: sync
2014-07-28 21:36:00 -06:00
84eb146e0a
kc705: add ddram pins
2014-07-28 21:35:18 -06:00
fe1c4535d0
mibuild.xilinx_vivado: support settingsXX.sh
...
* in the process refactor the version search, the architecture bit width
detection, the settings search and all also for xilinx_ise
* use distutils.version.StrictVersion
2014-07-27 19:50:15 -06:00
44c6e524ba
migen.fhdl.structure: add Signal.like(other)
...
This is a convenience method. Signal(flen(other)) is used frequently but that
drops the signedness. Signal((other.nbits, other.signed)) would be correct but
is long.
2014-07-24 23:52:59 -06:00
9fcea6e64a
migen/sim/generic: use kwargs to pass parameters to icarus.Runner
2014-07-24 10:17:54 -06:00
10d639d313
flow.plumbing: spelling
2014-07-19 14:29:51 -06:00
9266e10cae
flow.plumbing: make argument order consistent
2014-07-19 14:29:50 -06:00
ff1d105c7e
genlib/SyncFIFO: remove flush signal (use InsertReset instead)
2014-07-17 19:15:45 -06:00
a53feba8a1
mibuild/platforms: add APF27 and APF51 Armadeus platforms
2014-07-11 11:07:54 -06:00
f45897c97f
mibuild/generic_platform.py: adding ability to use void pins (none fpga pin) for connectors
...
Signed-off-by: Fabien Marteau <fabien.marteau@armadeus.com>
2014-07-09 10:41:51 +02:00
8349543732
style
2014-07-05 18:56:20 +02:00
2bb821c571
crt-or1k: trim useless exception vectors
2014-07-05 18:53:23 +02:00
9a64309fcd
Merge branch 'master' of github.com:m-labs/misoc
2014-07-04 10:29:53 +02:00
6462ee7fe1
Upgrade mor1kx. This fixes the UART bug that was due to IRQ 0 and 1 being non-maskable.
2014-07-04 10:29:42 +02:00
d4833cb3dc
cpuif: remove limitations on csr data_width
2014-06-28 17:39:55 +02:00
506ac0f780
Merge branch 'master' of github.com:m-labs/migen
2014-06-28 16:15:20 +02:00
f6dfabf7a9
mibuild/xilinx_vivado.py: add set property to misc constraint
2014-06-28 16:15:07 +02:00
a0df5baa55
host: add support for various csr_data width (8 & 32 tested, but should work with others)
2014-06-26 13:22:21 +02:00
af9f76f73a
Merge branch 'master' of github.com:m-labs/migen
2014-06-22 15:34:02 +02:00
ea0f4706f5
fsm: set reset_state as default state
2014-06-22 15:21:22 +02:00
0f9bc5ad6e
fix bit inversion on CSV/PY exports
2014-06-21 19:06:47 +02:00
7ad1028f8b
mibuild: use SimpleCRG instead of CRG_SE, remove period parameter for CRG_DS, clean up platforms
2014-06-20 17:29:29 +02:00
074a12b444
create dump class and specific export functions, add python dictionnary export
2014-06-19 13:24:47 +02:00
a737358919
host: split read/export and add csv export
2014-06-17 11:25:10 +02:00
4c426b36f3
fifo: add support for depth=2
2014-06-15 23:58:46 +02:00
70a2ee4368
migen/bank/description: add reset parameter to CSRStatus
2014-06-15 23:54:38 +02:00
e5ca0c5ed5
make.py: add platform-option
2014-06-07 13:43:23 +02:00
26717a49fe
kc705: use string default arg
2014-06-07 13:41:46 +02:00
be0d86f57f
initial Vivado support
2014-06-07 12:24:28 +02:00
8719206a3a
uart2wishbone: add default baudrate
2014-06-05 15:13:20 +02:00
4c2a2090b1
libbase: remove crt during make clean
2014-06-01 23:17:43 +02:00
ac97815619
targets/simple: pass kwargs
2014-05-24 11:29:03 +02:00
b26ac465bd
crt0: remove macadress for or1k as well
2014-05-24 10:43:50 +02:00
6deeca064f
bios/crt0.S: remove unused macaddr, add syscall handler stub
2014-05-24 10:41:54 +02:00
81ed92d3b9
spiflash: redundant slice
2014-05-24 10:39:07 +02:00
d3b96a0a33
programmer: make xc3sprog verbose
2014-05-24 10:39:02 +02:00
ed902bfcdf
crt: add umoddi3
2014-05-24 10:38:55 +02:00
b94cba2d4b
mila: add input pipe to ease timing
2014-05-24 09:23:16 +02:00
dc2024f54d
bios: remove references to 'DDR' SDRAM, as we also support SDR SDRAM
2014-05-23 21:31:26 +02:00
e9b49ebb44
Use SDRAM on the Papilio Pro
...
Based on code by Robert Jordens
2014-05-23 21:26:09 +02:00
31e142fd88
drivers: clean up / fixes
2014-05-22 18:33:28 +02:00
9a059336bf
storage: simplify run length encoder...
2014-05-22 18:13:27 +02:00
0bc1cd6f77
fix uart selection when opening wishbone
2014-05-22 16:11:32 +02:00
1dcbb077fd
make.py: init bios memory in build-bitstream action otherwise it is not possible to run clean or build-csr-csv or build-headers without build-bios
2014-05-21 21:16:06 +02:00
Florent Kermarrec
Yann Sionneau
Sebastien Bourdeauducq
Robert Jordens
Fabien Marteau