Florent Kermarrec
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69009c8405
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mila: test rle
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2013-09-22 21:23:51 +02:00 |
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Florent Kermarrec
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980a83a74c
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move trigger/recorder
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2013-09-22 11:46:02 +02:00 |
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Florent Kermarrec
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ce9bff21e9
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refactoring
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2013-09-22 02:49:59 +02:00 |
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Florent Kermarrec
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492a5acfe3
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add Run Length Encoding
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2013-03-23 22:06:08 +01:00 |
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Florent Kermarrec
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b1cbfe2326
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clean up/fixes
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2013-03-22 11:31:21 +01:00 |
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Florent Kermarrec
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87336128a3
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sim: update
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2013-02-26 23:25:10 +01:00 |
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Florent Kermarrec
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e95e8b03b7
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- reworking WIP
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2013-02-22 16:40:49 +01:00 |
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Florent Kermarrec
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e6042c122c
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adapt migScope to Migen changes
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2013-01-03 01:46:39 +01:00 |
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Florent Kermarrec
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4a59b63151
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Clean up
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2012-09-09 23:46:26 +02:00 |
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Florent Kermarrec
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b8eaf0906a
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Clean up
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2012-09-09 20:51:15 +02:00 |
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Florent Kermarrec
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2092c5a138
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add global tb, fix bugs
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2012-09-09 20:38:01 +02:00 |
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Florent Kermarrec
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2abd7f664d
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add tb_RecorderCsr.py
fixs in recorder.py
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2012-08-27 00:44:26 +02:00 |
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Florent Kermarrec
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d34c877401
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split migScope to trigger & recorder
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2012-08-26 21:30:23 +02:00 |
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Florent Kermarrec
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a99a902fef
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add vcd generator
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2012-08-26 20:56:56 +02:00 |
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Florent Kermarrec
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97cca81e0c
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tb_TriggerCsr.py : use truth table generator for Sum Lut
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2012-08-26 15:44:43 +02:00 |
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Florent Kermarrec
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bf7864104a
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tb_spi2Csr: Add clk_ratio
tb_spi2Csr: Add Read
spi2Csr : fixs
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2012-08-26 13:03:11 +02:00 |
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Florent Kermarrec
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2e54001fc1
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- fix Spi2Csr mistakes
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2012-08-25 23:29:23 +02:00 |
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Florent Kermarrec
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b5a44f2e98
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add sim: tb_Spi2Csr.py (skeleton, WIP)
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2012-08-25 21:53:06 +02:00 |
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Florent Kermarrec
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d14ffb9146
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add sim: tb_TriggerCsr.py
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2012-08-25 18:46:58 +02:00 |
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Florent Kermarrec
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f4cac2c102
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Add simulation skeleton
Remove SRLC16E, will be replaced by distributed ram
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2012-08-22 23:59:00 +02:00 |