9 commits

Author	SHA1	Message	Date
Sebastien Bourdeauducq	70ffe86356	New migen.fhdl.std to simplify imports + len->flen	2013-05-22 17:11:09 +02:00
Sebastien Bourdeauducq	b38818eb17	examples/sim/fir: convert to new API	2013-03-19 11:46:27 +01:00
Sebastien Bourdeauducq	51bec340ab	sim: remove PureSimulable (superseded by Module)	2013-03-15 19:41:30 +01:00
Sebastien Bourdeauducq	3a591c358c	examples/fir: better filter	2013-02-22 23:19:56 +01:00
Sebastien Bourdeauducq	f9acee4e68	corelogic -> genlib	2013-02-22 23:19:37 +01:00
Sebastien Bourdeauducq	92b67df41c	sim: default runner to Icarus Verilog	2013-02-09 17:04:53 +01:00
Sebastien Bourdeauducq	50ed73c937	New specification for width and signedness	2012-11-29 21:22:38 +01:00
Sebastien Bourdeauducq	5bf19c155f	sim: ensure clean IPC shutdown	2012-08-05 00:16:11 +02:00
Sebastien Bourdeauducq	973c00938d	Reorganize examples folder	2012-06-12 17:49:50 +02:00

Renamed from examples/fir.py (Browse further)