Sebastien Bourdeauducq
|
66fe45ba96
|
k7ddrphy: decrease CAS latency to account for cmd/data flight time
|
2014-08-22 18:46:01 +08:00 |
|
Sebastien Bourdeauducq
|
b94647ab16
|
k7ddrphy: suppress idiotic bitgen warning about ISERDES IOBDELAY parameter
|
2014-08-22 18:45:25 +08:00 |
|
Sebastien Bourdeauducq
|
402c7db63c
|
platforms/kc705: read the configuration flash faster (ISE only)
|
2014-08-22 18:44:10 +08:00 |
|
Sebastien Bourdeauducq
|
cb5894b33c
|
platforms: add -w option to bitgen_opt
|
2014-08-22 18:26:25 +08:00 |
|
Sebastien Bourdeauducq
|
35327a427f
|
targets/kc705: BIOS XIP
|
2014-08-22 17:13:10 +08:00 |
|
Sebastien Bourdeauducq
|
6b35c7b8ea
|
targets/ppro: reduce SPI flash clock frequency
|
2014-08-22 15:24:14 +08:00 |
|
Sebastien Bourdeauducq
|
7b10f1821f
|
targets/ppro: fix BIOS address
|
2014-08-22 15:24:00 +08:00 |
Florent Kermarrec
|
3eabec28cd
|
make.py: add set_flash_proxy_dir to flash-bios
|
2014-08-22 15:04:50 +08:00 |
|
Sebastien Bourdeauducq
|
2f2a57dd34
|
targets/ppro: clean up indentation
|
2014-08-22 14:41:28 +08:00 |
|
Florent Kermarrec
|
7f4e51253e
|
kc705: add spiflash pins
|
2014-08-22 10:32:58 +08:00 |
|
Florent Kermarrec
|
c19d134978
|
vivado: enable bitstream compression (optional)
|
2014-08-21 20:22:08 +08:00 |
Robert Jordens
|
bd232f3f61
|
fhdl.structure: do not permit clock domain names that start with numbers
|
2014-08-18 11:01:56 +08:00 |
|
Robert Jordens
|
ac2e961618
|
fhdl.structure: remove unused imports
|
2014-08-18 11:01:56 +08:00 |
|
Robert Jordens
|
6036fffef2
|
Signal.__getitem__: raise TypeError and IndexError when appropriate
|
2014-08-18 11:01:56 +08:00 |
|
Robert Jordens
|
b3d69913cd
|
Signal.like: pass kwargs
|
2014-08-18 11:01:56 +08:00 |
|
Robert Jordens
|
7e77254c57
|
vivado: make tcl a list of commands, add reporting
|
2014-08-18 11:01:56 +08:00 |
|
Florent Kermarrec
|
1c381acc6f
|
k7ddrphy: fix read_latency (CL is 2 sys_clk since we use quarter rate)
|
2014-08-14 22:46:06 +08:00 |
|
Florent Kermarrec
|
acbba37f5f
|
k7ddrphy: set bitslip to 0 on ISERDESE2 (needed at least for sim)
|
2014-08-14 22:46:06 +08:00 |
|
Florent Kermarrec
|
2e4bfe154f
|
k7ddrphy: add ODELAYE2 on dm path to match dq path (ODELAYE2 even configure with a delay of 0 generates a delay)
|
2014-08-14 22:46:06 +08:00 |
|
Florent Kermarrec
|
bb85f29f91
|
k7ddrphy: fix write_latency and take care of OSERDESE2 latency on oe
|
2014-08-14 22:46:06 +08:00 |
|
Florent Kermarrec
|
85b29c883a
|
sdramphy/initsequence: fix and add format_mr0 function
|
2014-08-14 14:17:54 +08:00 |
|
Florent Kermarrec
|
9844c25df9
|
k7ddrphy: add SERDES reset
|
2014-08-14 14:16:41 +08:00 |
|
Florent Kermarrec
|
194a5a0491
|
lasmicon: fix reset_n level
|
2014-08-14 14:15:48 +08:00 |
|
Sebastien Bourdeauducq
|
3a960e9e6a
|
flash_extra: use new programmer
|
2014-08-09 14:39:38 +08:00 |
|
Sebastien Bourdeauducq
|
a6c55d8dde
|
make.py: do not use prog.needs_flash_proxy
|
2014-08-09 14:38:56 +08:00 |
|
Sebastien Bourdeauducq
|
4d2623a87e
|
mor1kx: sync
|
2014-08-09 14:32:57 +08:00 |
|
Sebastien Bourdeauducq
|
c61f96588a
|
mibuild/programmer: remove unneeded needs_flash_proxy attr
|
2014-08-09 14:28:15 +08:00 |
|
Sebastien Bourdeauducq
|
c8dd4d2b40
|
k7ddrphy: send rddata_valid on all phases
|
2014-08-09 11:00:13 +08:00 |
|
Sebastien Bourdeauducq
|
54c63275e0
|
platforms/kc705: remove DDR3 multirank pins
|
2014-08-09 10:56:59 +08:00 |
|
Sebastien Bourdeauducq
|
60706e4b70
|
bus/dfi: add CKE and RESET_N
|
2014-08-09 10:56:08 +08:00 |
|
Sebastien Bourdeauducq
|
41c8c172b5
|
targets/kc705: integrate DDR3
|
2014-08-08 21:58:41 +08:00 |
|
Sebastien Bourdeauducq
|
0ebdf2be6d
|
bios/sdram: cleanup
|
2014-08-08 21:57:58 +08:00 |
|
Sebastien Bourdeauducq
|
b61dced909
|
bios/sdram: set ODT and RESET_N through DFII
|
2014-08-08 21:57:42 +08:00 |
|
Sebastien Bourdeauducq
|
8deadc5760
|
dfii: drive ODT and RESET_N
|
2014-08-08 21:56:35 +08:00 |
|
Sebastien Bourdeauducq
|
1322c0484b
|
lasmicon: drive ODT and RESET_N
|
2014-08-08 21:55:34 +08:00 |
|
Sebastien Bourdeauducq
|
0550cbb3ce
|
lasmicon: add CWL to PHY settings
|
2014-08-08 21:55:12 +08:00 |
|
Sebastien Bourdeauducq
|
777ebb7875
|
sdramphy/gensdrphy: fix rddata_en generation
|
2014-08-08 21:41:07 +08:00 |
|
Sebastien Bourdeauducq
|
a2c7ff4c0c
|
sdramphy: initial K7 DDR3 support
|
2014-08-08 21:28:26 +08:00 |
|
Florent Kermarrec
|
293ac09673
|
sdramphy/bios: make sdrrd/sdrwr generic
|
2014-08-08 19:25:10 +08:00 |
|
Sebastien Bourdeauducq
|
cfc37a3fa5
|
sdramphy/initsequence: rewrite DDR3 initialization sequence
|
2014-08-08 19:15:05 +08:00 |
|
Sebastien Bourdeauducq
|
e8db842538
|
s6ddrphy: fix DFI interface data width computation
|
2014-08-08 19:14:15 +08:00 |
|
Sebastien Bourdeauducq
|
5fb221e7d9
|
typo
|
2014-08-06 23:58:09 +08:00 |
|
Sebastien Bourdeauducq
|
efb2466c7e
|
gensoc: add id for KC705
|
2014-08-06 23:53:51 +08:00 |
|
Sebastien Bourdeauducq
|
fb48b89bac
|
platforms/kc705: generate clocks for SDRAM
|
2014-08-06 23:53:26 +08:00 |
|
Sebastien Bourdeauducq
|
7ebf08db5e
|
mibuild/xilinx: connect CE on reset synchronizer FFs
|
2014-08-06 23:51:50 +08:00 |
|
Sebastien Bourdeauducq
|
b124a98d92
|
genlib: add reset synchronizer
|
2014-08-06 19:38:37 +08:00 |
|
Sebastien Bourdeauducq
|
ca6d6954c1
|
targets/ppro: use migen reset synchronizer
|
2014-08-06 19:38:11 +08:00 |
|
Sebastien Bourdeauducq
|
4d382328d5
|
mibuild/xilinx: share more code between ISE and Vivado, use special overrides with Vivado, merge xilinx_tools into xilinx_common
|
2014-08-06 19:26:00 +08:00 |
|
Florent Kermarrec
|
d1ff43faa7
|
gensoc/cpuif: do not generate access functions for registers > 64 bits
|
2014-08-04 22:38:19 +08:00 |
|
Florent Kermarrec
|
452a4a76f3
|
use verilog namespace to export mila configuration
|
2014-08-03 17:09:01 +02:00 |