8e6ffff37a
software/demo: Add flash boot image (.fbi) preparation to allow demo to be flashed to SPI Flash.
2022-07-05 19:10:27 +02:00
46fe550338
software: Rename mkmscimg to crcfbigen and do cosmetic cleanups.
2022-07-05 18:57:42 +02:00
12bbc0946a
build/generic_programmer: Ask bitstream presence check on load_bitstream error.
2022-07-05 17:57:16 +02:00
a285071154
tools/litex_sim: Remove csr.csv force and just use provided argument.
2022-07-05 17:32:12 +02:00
bf9e2aa9f8
build: Rename backend argument to build-backend and use lower case.
2022-07-05 17:29:50 +02:00
922ad10eaf
build/xilinx/ise: Variable rename
...
isemode => _isemode
mode => _mode
2022-07-05 16:29:08 +02:00
855b88c039
build/xilinx/ise: Fix ngdbuild_opt not honored
...
It was set after the build stage which is too late
2022-07-05 16:23:57 +02:00
30a7a1cf16
build/xilinx/ise: Fix Yosys flow
2022-07-05 16:12:41 +02:00
5796f30b18
build/xilinx/ise: Fix XST flow
2022-07-05 14:14:02 +02:00
91a115584f
Merge branch 'enjoy-digital:master' into master
2022-07-05 13:33:13 +02:00
4fef89af53
software/liblitesdcard/spisdcard: Update comment.
2022-07-05 11:29:05 +02:00
9f2b62d6e8
Merge pull request #1340 from fritzbauer/SDCardInitFix
...
Do not call spisdcard_select for CMD0.
2022-07-05 11:27:23 +02:00
767647bb29
Merge pull request #1352 from gregdavill/feature/trellis_freq
...
build/lattice/trellis: Add MCLK frequency option
2022-07-05 07:52:59 +02:00
ef58f68126
build/lattice/trellis: Fix float(freq) parsing
2022-07-05 09:24:30 +09:30
ee580f2ce8
soc/cores/video: Set data to 0 during blanking, thanks @suarezvictor.
...
See https://github.com/enjoy-digital/litex/issues/1349 .
2022-07-04 19:22:55 +02:00
b74bb90c48
build/lattice/trellis: Add MCLK frequency option.
2022-07-04 19:16:47 +02:00
4b320a6a45
build/osfpga: Fix and switch to Raptor toolchain/Gemini device.
2022-07-04 18:52:47 +02:00
19d20786e3
build/efinix/xilinx: Fix.
2022-07-04 18:52:25 +02:00
4a23261499
Merge pull request #1356 from enjoy-digital/generic_toolchain
...
Introduce GenericToolchain and switch to it for build backends.
2022-07-04 18:35:44 +02:00
dc6b81a13f
Merge branch 'master' into generic_toolchain
2022-07-04 18:35:26 +02:00
08d1c53b80
build/xilinx/ise: Apply #1346 .
2022-07-04 18:27:46 +02:00
46788f2d9c
integration/soc Add accessible_region to add_memory_buses
...
Enables CPUs to know which memory addresses are accessible via
the connected memory_bus.
2022-07-04 12:47:09 +02:00
eb0f00f295
build/generic_toolchain: _build -> build. All toolchains: override build only when required
2022-07-03 22:12:43 +02:00
1f1d9f5c0e
cpu/neorv32: Initial switch to neorv32_litex_core_complex.
...
Status:
- Minimal/Lite variants working; Standard/Full are not (Related to cache?).
- GHDL does not seems to be able to convert VHDL to Verilog and keep parametrization;
we'll have to implement a workaround to be able to select variant and enable debug.
2022-06-29 15:48:07 +02:00
8eae77a310
Merge pull request #1347 from enjoy-digital/ci-cpus
...
test/test_cpu: Re-enable cv32e40p/marocchino.
2022-06-29 11:52:27 +02:00
7388684232
integration/export/get_memory_x: Replace spi_flash with rom.
...
Even when ROM is stored in SPI Flash, ROM regions has to be created.
2022-06-29 11:19:52 +02:00
9c3663f3d2
test/test_cpu: Re-enable cv32e40p/marocchino.
2022-06-29 11:15:48 +02:00
b6d00238cb
build/efinix/efinity/run_script: platform -> self.platform.
2022-06-29 10:33:00 +02:00
7af59fe1f7
build/xilinx/vivado: synth_mode -> self._synth_mode.
2022-06-29 10:18:14 +02:00
bc6ce4b04b
Merge pull request #1346 from cklarhorst/master
...
build/xilinx/ise: Fix yosys flow
2022-06-29 10:16:06 +02:00
382ebbf661
build: efinix/efinity lattice/diamond osfpga xilinx/f4pga xilinx/ise xilinx/yosys_nextpnr -> GenericToolchain
2022-06-28 22:21:24 +02:00
a4bb65655c
build/generic_toolchain: store fragment. Reorder build_io_constraints and build_timing_constraints
2022-06-28 22:20:22 +02:00
aec8cd5339
build/xilinx/ise: Fix yosys flow
...
The top name changed in 2016 but only XST was changed.
2022-06-28 15:26:14 +02:00
ec9d1c4fd0
CI: Disable more CPUs.
2022-06-27 22:43:01 +02:00
f898423390
test/test_cpu: Diable mor1kx/picorv32 for now due to issue with newer Verilator.
2022-06-27 19:54:50 +02:00
60d0c4ddd4
ci: Compile/Install Verilator from sources (Required for updated Vexriscv-SMP).
2022-06-27 18:53:02 +02:00
4ff839900b
bios/cmd_litedram: Enable sdram_init/mr_write commands also for SDRAM.
2022-06-27 17:49:39 +02:00
c4e3962def
soc/add_etherbone: Expose IP Broadcast capability.
2022-06-27 15:46:57 +02:00
6541a6c93b
build: gowin lattice/diamond lattice/oxide lattice/radiant microsemi quicklogic move to GenericToolchain
2022-06-26 21:40:56 +02:00
1f9bf1bd06
build/generic_toolchain: build_dir, vns now members. Adds build_placement_constraints call. Write verilog ASAP
2022-06-26 21:39:29 +02:00
564c062074
build/xilinx/vivado: use GenericToolchain
2022-06-26 09:06:20 +02:00
8446c5b342
build/anlogic: use GenericToolchain
2022-06-26 09:05:58 +02:00
b75a6ba636
build/lattice/icestorm: move parse_device and pnr_opts to finalize method
2022-06-26 09:05:22 +02:00
418d0f3c0d
build/generic_toolchain: finalize() method: for toolchain specifics tasks one platform ready
2022-06-26 09:04:00 +02:00
83f3c42b89
build/sim/verilator: add (unused) backend parameter
2022-06-25 18:15:48 +02:00
4a3c19cedc
build/lattice/icestorm: add edalize as alternate backend
2022-06-25 17:10:23 +02:00
04617027f4
build/lattice/icestorm: refactor the build options string for yosys and NextPnr
2022-06-25 15:36:38 +02:00
c8b336957f
build/generic_toolchain, soc/integration/builder: introducing a backend argument and edalize as alternate backend
2022-06-25 15:22:30 +02:00
d1e610c400
build/{generic_toolchain, lattice/icestorm, lattice/trellis}: remove toolchain dependants parameters for build_io_constraints, build_timing_constraints, build_placement_constraints. Those must be intercepted at the level of the specific toolchain.
2022-06-24 21:11:31 +02:00
7117de0f1f
build/lattice/icestorm/trellis: Generate Yosys script in build_project.
2022-06-24 10:33:51 +02:00
Florent Kermarrec
Christian Klarhorst
Christian Klarhorst
Greg Davill
Gwenhael Goavec-Merou