8289e71ea7
tools/litex_sim: Remove ident_version (now provived by kwargs).
2022-01-18 17:18:50 +01:00
ae70023f0d
soc_core: Switch from --ident-version parameter to --no-ident-version.
...
Identifier version is enabled by default and we just need to allow user to easily disable it for determinist builds.
The custom --no-ident-version added to targets can then be avoided with this and this argument will
now be available on all targets.
2022-01-18 14:07:26 +01:00
07c7f664cf
integration/soc/add_sdram: Set default l2_cache_reverse value to False.
...
For correct operation of Framebuffer + CPU writes, l2_cache_reverse has to be
set to False on targets. Set it to False by default in LiteX to avoid this.
2022-01-18 11:34:12 +01:00
b958453105
soc/add_video_framebuffer: Use clock_faster_than_sys when equal.
2022-01-17 18:19:23 +01:00
15045e96f0
cores/video: Switch 1920x1080@60Hz pix_clk to 148.5MHz.
2022-01-17 18:19:19 +01:00
04e9af9fef
core/video/VideoS7GTPHDMIPHY: Swap R/B components.
2022-01-17 18:19:15 +01:00
3d3229fb49
Merge pull request #1166 from gsomlo/gls-fatfs-sd-sata
...
RFC: software/fatfs: allow sata, [spi]sdcard disk ops to co-exist
2022-01-17 10:59:57 +01:00
0eded56afa
CHANGES: Start listing changes since 2021.12.
2022-01-17 10:17:10 +01:00
5e86e14299
Merge pull request #1162 from sergachev/eos_s3_software
...
QuickLogic EOS S3 ARM software support
2022-01-17 09:53:30 +01:00
9f1a847e93
litex_setup: Add Marocchino CPU to full install.
2022-01-17 09:02:34 +01:00
1c82b20fcb
Merge pull request #1161 from stffrdhrn/or1k-marocchino
...
marocchino: Add initial support for new OpenRISC core
2022-01-17 08:59:30 +01:00
672d1dd741
build/xilinx/symbiflow: Align devices.
2022-01-17 08:17:04 +01:00
4a3cd561c4
Merge pull request #1165 from bl0x/digilent_cmod_a7
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digilent_cmod_a7: Add xc7a35tcpg236-1 symbiflow_device.
2022-01-17 08:12:10 +01:00
87bd29fec2
software/fatfs: allow sata, [spi]sdcard disk ops to co-exist
...
At the moment, sata and [spi]sdcard fatfs disk access methods
are mutually exclusive, as their names collide with each other.
Implement a DISKOPS structure with media-specific disk access
methods, and a way for the boot code to specifiy which media
type's methods to use when loading files into RAM at boot time.
Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
2022-01-16 20:14:52 -05:00
4aff26ccaf
tools/litex_json2dts_linux.py: add mmc voltage regulator
...
Add MMC voltage regulator, and reference it from the mmc node.
For now, all boards we know of provide a 3.3V fixed voltage to
their SDCard receptacles, either directly or via PMOD.
2022-01-16 19:53:36 -05:00
1011b817c8
bios/boot: fix width of sata `length` variable
2022-01-16 19:46:19 -05:00
27ccb3e776
cpu/serv: Add intial MDU support (mdu variant).
2022-01-16 19:58:09 +01:00
b42525b462
add missing newline
2022-01-16 12:55:54 +01:00
881d457fbe
digilent_cmod_a7: Add xc7a35tcpg236-1 symbiflow_device.
2022-01-16 12:15:50 +01:00
0ba065db8a
cores/cpu/eos_s3: enable software support
2022-01-15 17:23:56 +01:00
d4a53b4d6d
software/bios: make makefile more universal and compact
2022-01-15 17:23:07 +01:00
cf8545c8ef
software/bios: enable map file generation
2022-01-15 17:22:46 +01:00
f07fb4e1e3
cores/cpu: rename eos-s3 to eos_s3 for compatibility
2022-01-15 17:16:48 +01:00
00dfaa1740
software/bios: place eos s3 interrupt table at .text start when present
2022-01-15 17:15:25 +01:00
15a927bcc8
libcompiler_rt: add more arm math ops
2022-01-15 17:14:38 +01:00
db9d40a5a0
integration/soc: warn about overrides only on differences
2022-01-15 17:13:48 +01:00
f8863bb986
integration/soc: cleanup formatting and comments
2022-01-15 17:12:31 +01:00
0e87b9b9be
integration/builder: print missing key name
2022-01-15 17:09:11 +01:00
5992e1db8c
marocchino: Add initial support for new OpenRISC core
...
The Marocchino is a superscaler OpenRISC implementation which has
advanced features including 64-bit double FPU support.
Much of the python module here is copied form mor1kx like the *.S
and *.h files.
2022-01-15 07:30:46 +09:00
c3b94a347e
cpu/rocket: increase IRQ lines to 8
2022-01-14 17:08:15 -05:00
cdacba06d1
soc/add_spi_sdcard: Fix missing renaming when rst pin is present.
2022-01-14 19:16:31 +01:00
ffc96a5655
Merge pull request #1155 from tongchen126/master
...
litex/soc/software/bios/cmds/cmd_mem.c: add mem_cmp
2022-01-14 19:02:16 +01:00
96a9495d6a
soc/add_spi_sdcard: Add optional Tristate.
...
This is required on some boards where the SDCard is shared with other chips (ex ESP32 on ULX3S).
2022-01-14 15:01:13 +01:00
4475b978d5
Merge pull request #1159 from fjullien/fix_cmd_mem_write
...
bios: fix mem_write address increment
2022-01-14 13:53:41 +01:00
8f1d50525d
bios: fix mem_write address increment
2022-01-14 13:16:02 +01:00
1b9bdc57ac
litex/soc/software/bios/cmds/cmd_mem.c: add mem_cmp
2022-01-12 12:09:00 +08:00
add2746a54
tools/litex_cli: Rename wb to bus.
2022-01-11 14:54:18 +01:00
a8de9054a3
tools/litex_client: Allow passing CSR name to --read/--write to simplify use.
...
ex:
litex_cli --read ctrl_scratch
litex_cli --write ctrl_scratch 0x5aa55aa5
2022-01-11 14:53:09 +01:00
438bb0b570
sim: allow custom modules to be in custom path
...
If a project needs a custom verilator module, it can now
specifies the path where the module's directory is.
SimPlatform can now look for extra modules:
builder.build(
extra_mods = ["mymodule1", "mymodule2"],
extra_mods_path = os.path.abspath(os.getcwd()) + "/modules",
sim_config=sim_config
)
Modules must be subdirectories of extra_mods_path:
.
├── modules
│ ├── mymodule1
│ ├── mymodule2
│ ├── ...
2022-01-09 21:15:11 +01:00
a330e9fda5
cores/spi_flash: Deprecate SPI Flash MMAPed cores (Designs have been switched with LiteSPI).
2022-01-07 19:08:03 +01:00
30a99582ae
litex/compat: Fully deprecate up5kspram renaming. (Warning to suggest change has been here for > 1 year).
2022-01-07 18:40:12 +01:00
c46824153d
litex/compat: Fully deprecate soc_sdram (Warning to suggest change has been here for > 1 year).
2022-01-07 18:38:56 +01:00
c010a98719
cpu: Add default set_reset_address function to CPU that will be overrided by each CPU (avoid hasattr check).
2022-01-07 15:17:37 +01:00
cb13f71b56
build/openocd/stream: Add get_ir method and use it to compute IR and handle specific ECP5 case.
...
JTAG-UART/JTAGBone on ECP5 non longer requires --jtag-chain=49 command.
2022-01-07 11:39:05 +01:00
f404877353
soc/SoCBusHandler: Add io_regions_check attribute and and disable IO region check with CPUNone.
2022-01-07 10:47:47 +01:00
e0961d7cb1
cores/cpu: Add missing Gowin EMCU comment.
2022-01-07 10:46:58 +01:00
23214638e4
cores/cpu: Allow multiple calls to set_reset_address (= override) since reset_adress is not not necessarily known at SoC creation.
...
When booting from SPI Flash, things will be done in the following order:
- SoC creation.
- SPI Flash peripheral creation (with dynamic mapping).
- CPU reset address can then be set.
2022-01-07 09:07:34 +01:00
5c278ae437
cpu/rocket/core: Move IO Region (ROM/SRAM can't be in an IO Region).
2022-01-06 15:32:31 +01:00
23b9d73354
integration/soc: Improve mem_map overriding display.
2022-01-06 13:46:21 +01:00
5363d61859
Merge pull request #1151 from fjullien/fix_wb_slave_cache_configuration
...
soc: raise an error if adding a SoCRegion with incoherent cache configuration
2022-01-06 10:12:20 +01:00
Florent Kermarrec
Gabriel Somlo
Ilia Sergachev
Bastian Löher
Stafford Horne
Franck Jullien
tongchen126
Franck Jullien