I am working on testing out the patches from:
https://github.com/litex-hub/linux/pull/8
These linux patches take advantage of the sdcard interrupt to track when
transfers finish. However, it seems the interrupt is not being
connected to the CPU.
This patch does that by allowing us to directly register and
EventManager module with the irq handler.
With recent BIOS changes the default rom size on the mor1kx built just
passes over the 64k boundary and the build fails. Since the 128K
default is a soft limit and the ROM gets resized to the actual ROM
requirements this should be relatively safe.
Note, that if a RW rom is configured the full 128kb will be allocated.
Fixes: #893
When passed as str, the timing dict will be extracted from litex.soc.cores.video.video_timings.
When passed as tuple, custom dict will be directly passed to VTG.
The linker does not actually recognise -nodefaultlibs, that is a compiler
option.
Prior to binutils 2.36, ld treated -nodefaultlibs as a string of short
options and ignored them as unrecognised. Starting from binutils 2.36, it
reports an error instead:
riscv64-unknown-elf-ld: Error: unable to disambiguate: -nodefaultlibs (did you mean --nodefaultlibs ?)
See also: https://sourceware.org/bugzilla/show_bug.cgi?id=27050Fixes#825.
Adding wraps around capability will have to be discussed, if implemented this has to
be done very carefully since there are no relation between the total delay that can
be compensated through the I/O-DELAYs and the SDRAM clock period.
As implemented, it also produced confusing values in the logs:
m0:0 m1:0
Read leveling:
m0, b0: |00000000000000000000000000000000| delays: -
m0, b1: |00000000000011111111111111100000| delays: 19+-07
m0, b2: |00000000000000000000000000001111| delays: 14+-17
m0, b3: |00000000000000000000000000000000| delays: -
m0, b4: |00000000000000000000000000000000| delays: -
m0, b5: |00000000000000000000000000000000| delays: -
m0, b6: |00000000000000000000000000000000| delays: -
m0, b7: |00000000000000000000000000000000| delays: -
best: m0, b01 delays: 19+-07
m1, b0: |00000000000000000000000000000000| delays: -
m1, b1: |00000000000011111111111111000000| delays: 19+-07
m1, b2: |00000000000000000000000000001111| delays: 15+-17
m1, b3: |00000000000000000000000000000000| delays: -
m1, b4: |00000000000000000000000000000000| delays: -
m1, b5: |00000000000000000000000000000000| delays: -
m1, b6: |00000000000000000000000000000000| delays: -
m1, b7: |00000000000000000000000000000000| delays: -
best: m1, b01 delays: 19+-07
Switching SDRAM to hardware control.
--> 14+-17 and 15+-17 are confusing.
This is useful for long-running commands generally and in particular
for those without any data transfer, such as erase. It is a
level-sensitive interrupt because that makes it a little harder to
lose interrupts due to incorrect programming.
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
Bit 2 of the command register now tells the controller to wait while
the card is indicating that it is busy (by pulling the DAT0 line low).
The card can do this for commands 7 and 12 and app command 41 (and
also for commands 20, 28, 29, 38 and 43, but we don't use those here.)
This sets bit 2 for those commands.
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
Florent Kermarrec
Tim Callahan
Stafford Horne
Tim Ansell
Jędrzej Boczar
Dan Callaghan
Jan Luebbe
Karol Gugala
Paul Mackerras