Commit Graph

6323 Commits

Author SHA1 Message Date
Florent Kermarrec 1fca7b9a91 software/liblitesata/sata_read: handle errors. 2020-10-28 18:59:36 +01:00
Florent Kermarrec 2bb46b305b software/liblitesata: fix warning, typo, add TODO. 2020-10-27 09:39:01 +01:00
Florent Kermarrec c0ba03ef66 targets/kc705: add initial SATA support. 2020-10-26 15:14:40 +01:00
Florent Kermarrec 4127af36b5 soc/software: add initial minimal LiteSATA support (allow booting from SATA drive). 2020-10-26 15:13:56 +01:00
bunnie 37f2ebe675 add responder for type 0 cti, so that wb debug access works 2020-10-25 17:50:56 +08:00
Florent Kermarrec c474272f53 soc/interconnect/stream: comment reset_less on payload since cause issue with LiteSATA, understand why. 2020-10-23 14:33:24 +02:00
Florent Kermarrec e94876753d soc/cores/icap: add back missing add_csr (was missing after adding add_reload method). 2020-10-23 08:00:43 +02:00
Florent Kermarrec 0dec446434 tools/litex_client: add utils to dump FPGA identifier and registers and expose it as litex_cli.
Dump FPGA identifier: litex_cli --ident
Dump FPGA registers: litex_cli --regs
2020-10-22 17:45:45 +02:00
Florent Kermarrec 30b226f895 soc/intergration/export: additional name override fix. 2020-10-22 08:55:14 +02:00
enjoy-digital abdc8bb26e
Merge pull request #681 from Disasm/fix-svd-soc-name
Fix SoC name in SVD generator
2020-10-22 08:53:32 +02:00
Florent Kermarrec 4eb634ba2d soc/interconnect/csr: fix CSRAccess values check. 2020-10-21 21:43:08 +02:00
enjoy-digital e7b33a9ea8
Merge pull request #680 from daveshah1/dave/radiant-portname-fix
radiant: Use {} string for bus port names
2020-10-21 21:23:05 +02:00
enjoy-digital 7bbde6d05a
Merge pull request #679 from DurandA/patch-6
Add integer limits to stdint.h
2020-10-21 21:22:37 +02:00
Florent Kermarrec c430587e91 soc/interconnect/stream/Shifter: add shift signal as optional parameter. 2020-10-21 15:52:53 +02:00
Vadim Kaushan e4997295bd
Fix SoC name in SVD generator
The name was overwritten with one of the CSR region names
2020-10-21 16:40:35 +03:00
David Shah 66eb38cf84 radiant: Escape bus port names
Signed-off-by: David Shah <dave@ds0.me>
2020-10-21 14:05:33 +01:00
Florent Kermarrec 5a6b8f452d soc/interconnect/stream: add Shifter.
Useful to shift stream data (ex for SerDes alignment).
2020-10-21 12:47:55 +02:00
Florent Kermarrec ad04365e20 soc/cores/code_8b10b: add K helper. 2020-10-21 09:49:38 +02:00
Florent Kermarrec e91ec2ed83 soc/cores/code_8b10b: add StreamEncoder/Decoder (to be used with LiteX's streams).
With improvements to handle backpressure on non-continous streams.
2020-10-21 09:29:21 +02:00
Arnaud Durand eb26d09dbe Add integer limits to stdint.h 2020-10-21 01:48:29 +02:00
Florent Kermarrec 918a0d95ba platforms/targets: keep up to date with litex-boards. 2020-10-20 12:00:33 +02:00
enjoy-digital 84c358889d
Merge pull request #677 from madscientist159/master
Add initial interrupt support for Microwatt in LiteX
2020-10-20 08:56:39 +02:00
enjoy-digital 72140f6df9
Merge pull request #674 from daveshah1/radiant-yosys-synth
build/radiant: Allow synthesis with Yosys
2020-10-20 08:15:36 +02:00
Raptor Engineering Development Team 90d71ec247 Add initial interrupt support for Microwatt in LiteX
There is a conflict between the LiteX way of doing things and the POWER
way of handling interrupt tables.  LiteX expects to be able to put a ROM
at address 0 and load an application into RAM at a higher address; POWER
is architected to jump to exception handlers at 0x100...0x1000.

As a result of this, we have taken the approach of placing generic exception
handler entry / exit routines into ROM, and reserving a single pointer in
SRAM to determine the C ISR handler location.  If no application is loaded,
this pointer is set to the BIOS ROM ISR.  When an application loads, before
reenabling interrupts, it needs to set __rom_isr_address to the address of
the application's ISR, otherwise the BIOS ROM ISR will continue to be used.

Tested to operate with the built-in UART in IRQ mode, both in BIOS and in
loaded RAM application.
2020-10-16 14:49:05 -05:00
Raptor Engineering Development Team af82abb807 Allow SoCCore instances to set maximum interrupt number 2020-10-16 14:48:04 -05:00
Florent Kermarrec 288306c86a software/liblitedram: add initial Build-In Self-Test software.
To be used with LiteDRAM's BIST Generator/Checker, ex:

from litedram.frontend.bist import  LiteDRAMBISTGenerator, LiteDRAMBISTChecker
self.submodules.sdram_generator = LiteDRAMBISTGenerator(self.sdram.crossbar.get_port())
self.add_csr("sdram_generator")
self.submodules.sdram_checker = LiteDRAMBISTChecker(self.sdram.crossbar.get_port())
self.add_csr("sdram_checker")
2020-10-15 16:20:05 +02:00
bunnie d23b88f739
Merge pull request #675 from enjoy-digital/spi_opi_dq_oe_dq_copi
soc/cores/spi_opi: expose dq/dq_copi to allow constrainting them from…
2020-10-14 18:45:13 +08:00
Florent Kermarrec c6f7f0210a soc/cores/spi_opi: expose dq/dq_copi to allow constrainting them from design. 2020-10-14 10:31:29 +02:00
David Shah 15dc97476c build/radiant: Allow synthesis with Yosys
Signed-off-by: David Shah <dave@ds0.me>
2020-10-13 12:11:48 +01:00
enjoy-digital 4d553a6fc0
Merge pull request #672 from enjoy-digital/litedram_write_latency
Add dynamic write latency calibration to LiteDRAM.
2020-10-12 19:42:31 +02:00
Florent Kermarrec f0abc185e1 targets/sim: update sdram (manual cmd_latency no longer needed). 2020-10-12 18:47:09 +02:00
Florent Kermarrec bc68351475 software/liblitedram: use SDRAM_PHY_WRITE_LATENCY_CALIBRATION_CAPABLE flag. 2020-10-12 16:05:44 +02:00
Florent Kermarrec c596135274 bios/cmd/cmd_litedram: add sdram_test command. 2020-10-12 13:52:15 +02:00
Florent Kermarrec d4d4ca53b0 software/liblitedram/sdram.c: move activate/precharge to sdram_write_read_check_test_pattern, change second seed. 2020-10-12 13:00:44 +02:00
Florent Kermarrec d1f04e67c5 software/liblitedram: use 2 cycles increment on write bitslip (for tCK steps). 2020-10-12 10:58:43 +02:00
Florent Kermarrec 3d5bc29dd1 software/liblitedram: add initial write latency calibration. 2020-10-09 20:04:16 +02:00
Florent Kermarrec 3518223c84 software/liblitedram: add functions to simplify read_leveling and do the test with 2 seeds.
Doing the test with 2 seeds prevents the test to success if previous content in DRAM was
still the expected one (ex after a sdram_cal command that succeded).
2020-10-09 15:50:44 +02:00
Florent Kermarrec 69177c9251 software/liblitesdram: add initial support for write leveling bitslip (configurable via bios commands). 2020-10-08 19:38:57 +02:00
Florent Kermarrec 004924a319 soc/interconnect/csr: expose re on CSRStatus (to allow triggering actions on CSRStatus writes). 2020-10-08 11:34:57 +02:00
Florent Kermarrec b904aa7d18 libbase/memtest: simplify logs and add test size to memtest/memspeed banner. 2020-10-08 09:11:28 +02:00
Florent Kermarrec e4fe0d9ef4 soc/cores/spi_flash: fix with_bitbang=False compilation. 2020-10-07 19:32:10 +02:00
Florent Kermarrec 375b6f2dc7 soc/cores/spi_flash: fix Dual mode compilation. 2020-10-07 19:28:13 +02:00
Florent Kermarrec a2b71fde4a soc: change default CSR bus data-width to 32.
A CSR bus data-width of 32 has been validated on very various design and is
now recommended. It provides better performance without impacting resource
usage (even on iCE40).
2020-10-07 16:38:49 +02:00
Florent Kermarrec 4f30a5b8e5 libbase/memtest: add memtest_data_speed function that prints speed in B/KiB/MiB/GiB/s depending the value. 2020-10-07 13:01:14 +02:00
Florent Kermarrec 0a80e4c3d6 libbase/memtest: revert previous printf (the informations are provided below and this make it too verbose). 2020-10-07 12:42:58 +02:00
enjoy-digital 5e2a4efac6
Merge pull request #665 from fidergo-stephane-gourichon/more_precise_log
More precise memory performance test.
2020-10-07 12:38:44 +02:00
enjoy-digital 83b4447f0e
Merge pull request #662 from fidergo-stephane-gourichon/dfu-util_with_-R
Unconditionally ask dfu-util to "Issue USB Reset"
2020-10-07 12:37:53 +02:00
Florent Kermarrec 305092c7b8 test/test_icap: update. 2020-10-07 12:36:08 +02:00
Florent Kermarrec ad7671f811 soc/cores/icap/ICAP: add with_csr parameter and add_reload method to allow reloading the FPGA from the logic. 2020-10-06 17:38:39 +02:00
enjoy-digital 42025dcbfa
Merge pull request #666 from gsomlo/gls-sdcard-cd
bios: add command returning card-detect pin status
2020-10-06 10:31:25 +02:00