c227576f3d
add test_link.py (replace test_bist_mila)
2015-01-16 21:16:05 +01:00
175618bcb4
use csr_data_width of 32 to speed up data mila upload
2015-01-16 20:57:01 +01:00
d13366dd2d
bist: use hardware counter for speed calc and remove loops mode
2015-01-16 18:48:34 +01:00
1170a1070b
add need_reset from controller to request system reset when SATA is not locked
2015-01-15 00:56:47 +01:00
788546c6ae
add frontend and improve BIST
2015-01-14 15:47:13 +01:00
4deda89dcb
simplify bist
2015-01-07 22:15:57 +01:00
a450079866
command: add support for larger DMAs
2015-01-06 16:48:19 +01:00
8b1522bbc9
clean up TestDesign
2014-12-24 15:05:17 +01:00
74dd907503
add test_bist_mila to show how to capture data
2014-12-23 21:00:38 +01:00
db711edd89
add test_bist with mila
2014-12-23 20:41:35 +01:00
3e5a4ab097
add wr_only and rd_only mode to BIST (to test speed) and switch to 100MHz system clock
2014-12-23 20:41:13 +01:00
678ee33af4
improve BIST and clean up (remove support of identify command and debug code)
2014-12-23 19:27:52 +01:00
38d3f3697b
test bist at high speed(working)
2014-12-23 01:39:41 +01:00
46b2d02783
test bist at slow speed (working)
2014-12-23 00:41:39 +01:00
6b12782816
read/write seems OK with CommandGenerator
2014-12-23 00:08:22 +01:00
c17159754c
add test_read / test_write (HOST<-->HDD transfers OK for the 3 tests, rx data seems to be stuck in link of command layer)
2014-12-20 16:50:34 +01:00
eebc2abcda
add mode generic CommandGenerator for debug
2014-12-20 16:21:26 +01:00
f495639f22
add primitives decoding in test_identify to ease debug
2014-12-20 01:26:58 +01:00
ea2b06b285
fix phy datapath, first communications between SATACON and a HDD... :)
2014-12-19 22:20:41 +01:00
a79696641a
prepare identify test with SATACON
2014-12-19 19:05:49 +01:00
880c7e7ecc
test: change UART baudrate and test SATACONTRemover
2014-12-19 17:45:02 +01:00
4f22bc807a
make ctrl/datapath in phy vendor agnostics and simplify imports
2014-12-18 19:45:21 +01:00
bcc0be10ee
phy: use vivado parameters and fix RX datapath (LSB first)
2014-12-17 23:49:55 +01:00
0f8f89a269
update clock constraints for SATA1 and use sys_clk of 200MHz
...
- data seems stable (mila capture) except when receive the ALIGN primtive from the device, we should maybe disable alignment on the HOST when link is ready...
2014-12-17 19:24:23 +01:00
5a16a5b46d
add very basic PHY stimulator (to see HDD behaviour when we send primitives)
2014-12-17 17:57:37 +01:00
3f7406a937
various fixes and simplifications, SATA1 & SATA2 OK
2014-10-28 02:15:19 +01:00
f5001751d0
instanciate GTXE2_COMMON (seems recommended in AR43339)
2014-09-30 10:57:52 +02:00
cf084fd079
test to visualize OOB with Miscope
2014-09-30 10:17:15 +02:00
7e31ef2152
init with repo with simple TestDesign
2014-09-22 13:36:43 +02:00
Florent Kermarrec