Commit Graph

5200 Commits

Author SHA1 Message Date
Florent Kermarrec c304c4db27 targets/icebreaker: add description of the board, link to crowdsupply campagin and to the more complete example. 2020-03-13 09:37:42 +01:00
Sean Cross b5bddc2332
Merge pull request #426 from esden/update-wavedrom
Updating the vendored wavedrom js files.
2020-03-13 13:44:13 +08:00
Piotr Esden-Tempski d063acb767 Updating the vendored wavedrom js files. 2020-03-12 22:35:04 -07:00
Florent Kermarrec a27385a79c soc/intergration: rename mr_memory_x parameter to memory_x. 2020-03-12 12:20:48 +01:00
enjoy-digital d5da9e0df4
Merge pull request #424 from esden/generate-memory-x
Add --mr-memory-x parameter to generate memory regions memory.x file
2020-03-12 12:12:48 +01:00
Piotr Esden-Tempski 4d02263223 Add --mr-memory-x parameter to generate memory regions memory.x file.
This file is used by rust embedded target pacs.
2020-03-11 18:12:18 -07:00
Florent Kermarrec e9f0ff68ce Merge branch 'master' of http://github.com/enjoy-digital/litex 2020-03-11 12:57:29 +01:00
Florent Kermarrec 979f98ea31 software: revert LTO changes (Disable it).
It seems LTO is not yet fully working with all configurations, so it's better
reverting the changes for now.
- cause issues with LM32 available compilers.
- seems to cause issues with min/lite variant of VexRiscv.
- seems to cause issues with some litex-buildenv configurations. (see https://github.com/enjoy-digital/litex/issues/417).
2020-03-11 12:57:00 +01:00
Sean Cross 01b6969375
Merge pull request #422 from xobs/core-doc-fixes
Core doc fixes
2020-03-11 19:38:42 +08:00
enjoy-digital 4ccf62afc1
Merge pull request #423 from gsomlo/gls-ethmac-fixes
integration/soc: add_ethernet: honor self.map["ethmac"], if present
2020-03-11 12:33:50 +01:00
Florent Kermarrec bb8905fa5d cores/gpio: add CSR descriptions. 2020-03-11 12:06:15 +01:00
Florent Kermarrec 4dabc5a625 cores/icap: add CSR descriptions. 2020-03-11 11:04:42 +01:00
Florent Kermarrec 77132a48b0 cores/spi: add CSR descriptions. 2020-03-11 10:58:32 +01:00
Florent Kermarrec 6d861c6e57 cores/pwm: add CSR descriptions. 2020-03-11 10:38:28 +01:00
Florent Kermarrec cbc1f5949d cores/xadc: add CSR descriptions. 2020-03-11 10:05:14 +01:00
Gabriel Somlo a904034811 integration/soc: add_ethernet: honor self.map["ethmac"], if present
Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
2020-03-10 19:49:34 -04:00
Florent Kermarrec 846a2720b7 targets/kcu105: move cd_pll4x. 2020-03-10 17:02:28 +01:00
Florent Kermarrec c97fabb285 targets/kcu105: simplify CRG using USIDELAYCTRL. 2020-03-10 16:48:07 +01:00
Florent Kermarrec 3c0b97eec8 cores/clock/USIDELAYCTRL: use separate reset/ready counters and set cd_sys.rst internally.
This is the behaviour that was duplicated in each target. Integrating it here
will allow simplifying the targets.
2020-03-10 16:46:54 +01:00
Sean Cross a2f61b4e80 soc/cores/spi_opi: documentation fixes
The ModuleDoc-generated documentation for the spi_opi module produced
slightly invalid output due to ambiguities in how rst assigns headers.
As a result, sections from the spi_opi document would appear as full
sections.

This cleans up these errors so that it parses properly under sphinx.

Signed-off-by: Sean Cross <sean@xobs.io>
2020-03-10 20:40:04 +08:00
Sean Cross d2f6139dc7 soc/cores/i2s: fix rst parsing errors
The ModuleDoc-generated documentation for the i2s module produced
slightly invalid output due to ambiguities in how rst assigns headers.
As a result, sections from the i2s document would appear as full
sections.

This cleans up these errors so that it parses properly under sphinx.

Signed-off-by: Sean Cross <sean@xobs.io>
2020-03-10 20:37:55 +08:00
Florent Kermarrec bcbf558b6b bios: add more Ultrascale SDRAM debug with sdram_cdly command to set clk/cmd delay. 2020-03-10 13:08:49 +01:00
enjoy-digital c4ce6da6c8
Merge pull request #419 from gsomlo/gls-ultra-sdram-fixup
software/bios: fixup for Ultrascale SDRAM debug
2020-03-10 11:43:23 +01:00
Florent Kermarrec b509068790 cores/clock: add logging to visualize clkin/clkouts and computed config. 2020-03-10 11:13:16 +01:00
Florent Kermarrec 04b8a91255 integration/soc: add FPGA device and System clock to logs. 2020-03-10 11:10:23 +01:00
Florent Kermarrec 02cba41d64 targets/icebreaker: create CRG after SoC. 2020-03-10 11:09:56 +01:00
Gabriel Somlo 4d15e1f7f8 software/bios: fixup for Ultrascale SDRAM debug
Keep CSR accesses independent of csr_data_width and csr_alignment.

Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
2020-03-09 15:32:08 -04:00
Florent Kermarrec ba2f31d43d integration/soc: set use_rom when cpu_reset_address is defined in a rom region. 2020-03-09 19:36:47 +01:00
Florent Kermarrec 8808c884c5 boards/platforms/icebreaker: cleanup a bit. 2020-03-09 19:16:02 +01:00
Florent Kermarrec 4656b1b2ad software/common: fix LTO checks. 2020-03-09 19:08:27 +01:00
Florent Kermarrec 2a91deadcb soc/cores/clock/iCE40PLL: add SB_PLL40_PAD support. 2020-03-09 19:03:05 +01:00
Florent Kermarrec 38d7f8a6e6 build/lattice/icestorm: add timingstrict parameter and default to False. (similar behavior than others backends) 2020-03-09 19:02:23 +01:00
Florent Kermarrec 1e9aa64387 targets/icebreaker: simplify, use standard VexRiscv, add iCE40PLL and run BIOS from SPI Flash. 2020-03-09 19:01:16 +01:00
Florent Kermarrec 197bdcb026 lattice/icestorm: enable DSP inference with Yosys and avoid setting SPI Flash in deep sleep mode after configuration which prevent running ROM CPU code from SPI Flash. 2020-03-09 16:51:18 +01:00
Florent Kermarrec 37869e38b8 boards: add initial icebreaker platform/target from litex-boards. 2020-03-09 11:56:55 +01:00
Florent Kermarrec 72af1b39eb software/bios: add Ultrascale SDRAM debug functions. 2020-03-09 10:55:31 +01:00
Florent Kermarrec 6480d1803e boards/platforms/kcu105: avoid unnecessary {{}} on INTERNAL_VREF. 2020-03-09 09:37:31 +01:00
Florent Kermarrec b02c23391a integration/soc/SoCRegion: add size_pow2 and use this internally for checks since decoder is using rounded size to next power or 2. 2020-03-08 19:17:31 +01:00
Florent Kermarrec e801dc0261 soc: allow creating SoC without BIOS.
By default the behaviour is unchanged and the SoC will provide a ROM:
./arty.py

Bus Regions: (4)
rom                 : Origin: 0x00000000, Size: 0x00008000, Mode: R, Cached: True Linker: False
sram                : Origin: 0x01000000, Size: 0x00001000, Mode: RW, Cached: True Linker: False
main_ram            : Origin: 0x40000000, Size: 0x10000000, Mode: RW, Cached: True Linker: False
csr                 : Origin: 0x82000000, Size: 0x00010000, Mode: RW, Cached: False Linker: False

The integrated rom can be disabled with:
./arty.py --integrated-rom-size=0

but the SoC builder will check for a user provided rom, and if not provided will complains:
ERROR:SoC:CPU needs rom Region to be defined as Bus or Linker Region.

When a rom is provided, the CPU will use the rom base address as cpu_reset_address.

If the user just wants the CPU to start at a specified address without providing a rom,
the cpu_reset_address parameter can be used:

./arty.py --integrated-rom-size=0 --cpu-reset-address=0x01000000

If the provided reset address is not located in any defined Region, an error will
be produced:
ERROR:SoC:CPU needs reset address 0x00000000 to be in a defined Region.

When no rom is provided, the builder will not build the BIOS.
2020-03-06 20:05:27 +01:00
enjoy-digital 5ded144762
Merge pull request #416 from enjoy-digital/csr_svd
Add SVD export capability to Builder (csr_svd parameter) and targets …
2020-03-06 19:00:13 +01:00
Florent Kermarrec ecca3d801d integration/builder: rename software methods to _prepare_rom_software/_generate_rom_software/_initialize_rom_software. 2020-03-06 14:53:59 +01:00
Florent Kermarrec 69ffafd81d integration/builder: generate csr maps before compiling software. 2020-03-06 14:20:32 +01:00
Florent Kermarrec e2dab06386 Add SVD export capability to Builder (csr_svd parameter) and targets (--csr-svd argument) and fix svd regression.
This allows generating SVD export files during the build as we are already doing for .csv or .json.

Use with Builder:
builder = Builder(soc, csr_svd="csr.svd")

Use with target:
./arty.py --csr-svd=csr.svd
2020-03-06 14:12:58 +01:00
Florent Kermarrec e124aed9a2 software/common.mak: fix LTO refactoring issue. 2020-03-05 23:42:36 +01:00
enjoy-digital 8bfb845f9c
Merge pull request #412 from antmicro/fix-copyrights
Fix copyrights
2020-03-05 19:05:02 +01:00
Karol Gugala da580e31fd Fix copyrights
Signed-off-by: Karol Gugala <kgugala@antmicro.com>
Signed-off-by: Mateusz Holenko <mholenko@antmicro.com>
2020-03-05 17:44:10 +01:00
enjoy-digital 361b6a068b
Merge pull request #408 from gsomlo/gls-fix-nexys-sdcard
targets/nexys4ddr: fix sdcard clocker initialization
2020-03-05 15:22:40 +01:00
Gabriel Somlo 020bef4197 targets/nexys4ddr: fix sdcard clocker initialization 2020-03-05 09:02:29 -05:00
enjoy-digital 9249fc90cf
Merge pull request #410 from antmicro/netv2-edid
platform/netv2: add proper I2C pins for HDMI IN0
2020-03-05 11:43:02 +01:00
Piotr Binkowski 72f63243cd platform/netv2: add proper I2C pins for HDMI IN0 2020-03-05 11:27:47 +01:00